Monolithic Power Systems Inc. MPQ8623GD-Z

Overview

MPQ8623GD-Z from Monolithic Power Systems is a fully integrated, high-frequency synchronous step-down converter delivering up to 6A output current with adjustable current limit, 0.9V–6V programmable output voltage, and selectable 600/1100/2000kHz switching frequency. It employs adaptive constant-on-time (COT) control for ultrafast transient response and operates across 4V–16V input range with internal 3V LDO biasing. Used in telecom PoL, server VRMs, and GPU power rails.

For engineers reviewing the MPQ8623GD-Z datasheet, MPQ8623GD-Z pinout, MPQ8623GD-Z application, or MPQ8623GD-Z equivalent, key selection criteria include its programmable current limit (via CS pin), PGOOD open-drain status signaling, TRK/REF-based output tracking, pre-bias start-up capability, and QFN-14 (2mm×3mm) thermal performance with θJB = 6.8°C/W.

Technical Context

The MPQ8623GD-Z implements an internally compensated adaptive COT control architecture that dynamically adjusts ramp compensation to maintain stability across full VIN/VOUT ranges without external loop components. Its valley-current sensing via CS pin enables cycle-by-cycle over-current protection with programmable trip threshold (1.15–1.25V) and latch-off fault recovery.

It integrates dual MOSFETs with RDS(ON) of 22.6mΩ (HS) and 8.1mΩ (LS) at 25°C, supports forced CCM or pulse-skip light-load operation via MODE pin configuration, and features output discharge FET (RON ≈ 80Ω) activated during EN deassertion to rapidly collapse pre-biased outputs.

Key Specifications

Pinout & Package

MPQ8623GD-Z is housed in a thermally enhanced QFN-14 package (2mm × 3mm, 0.5mm pitch) with exposed PGND pad for low-impedance thermal and electrical grounding. The package supports reflow soldering per JEDEC J-STD-020 and achieves θJB = 6.8°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MPQ8623GP-AEC1, the MPQ8623GD-Z trades automotive qualification for lower unit cost and standard commercial qualification, while MPQ8632GQ-AEC1 delivers double the current capacity at the expense of higher BOM cost and larger inductor requirements - making MPQ8623GD-Z the preferred choice for 6A PoL applications where AEC-Q100 is unnecessary.

Availability

MPQ8623GD-Z is available at Aetrix Electronics and suitable for telecom point-of-load, server VRM core supplies, and GPU memory rail designs requiring stable component supply, RoHS-compliant packaging, and lead-free assembly compatibility.

Supply support for MPQ8623GD-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ8623 belongs to MPS's high-efficiency synchronous buck converter product line, engineered for compact, high-current DC/DC conversion in space-constrained infrastructure and computing applications where thermal performance and transient response are critical.

FAQ

What is the minimum recommended input voltage for MPQ8623GD-Z with internal VCC bias?

The minimum input voltage is 4V when using internal VCC bias. Below this, the internal 3V LDO cannot regulate properly, causing UVLO activation and disabling the converter. External 3.3V VCC bias allows operation down to 2.85V input, but requires additional bias supply routing and decoupling.

How does the TRK/REF pin affect soft-start timing and output tracking?

TRK/REF sets both functions: its capacitor value determines soft-start duration (e.g., 1nF = 1.5ms, 10nF ≈ 4.5ms), and when driven externally (0.3–1.4V), it replaces the internal 900mV reference to force output tracking. During startup, TRK/REF must reach ≥900mV before regulation begins, ensuring monotonic ramp behavior.

Can MPQ8623GD-Z operate without an external bootstrap capacitor?

No. A 0.1µF ceramic capacitor between BST and SW is mandatory to generate the floating gate drive voltage for the high-side MOSFET. Omitting it causes immediate HS-FET failure due to insufficient gate-source voltage, resulting in no switching and potential thermal damage.

What happens during pre-bias start-up when the output is already charged to 1.2V?

The MPQ8623GD-Z disables both HS- and LS-FETs until the TRK/REF capacitor voltage exceeds the sensed FB voltage. If BST voltage falls below 2.3V during this period, narrow LS-FET pulses charge BST through VCC, minimizing output droop. This ensures monotonic rise without reverse current or oscillation.

Is the PGOOD signal functional when VIN drops below UVLO threshold?

Yes - PGOOD is actively clamped to ~0.7V (not tri-stated) when VIN fails to power the IC, even with external pull-up. This provides unambiguous fault indication to host controllers, distinguishing input failure from output undervoltage events which cause PGOOD to latch low at 80% VREF.

How is the current limit threshold calculated for a 5.5A target using the CS pin?

Using Equation (4) and VOCP = 1.2V, GCS = 40µA/A: RCS = (1.2V) / (40µA/A × 5.5A) = 5.45kΩ. Table 2 confirms 5.49kΩ yields 5.5A, accounting for process variation. A 1% tolerance resistor (e.g., 5.49kΩ ±1%) ensures trip accuracy within ±5% over temperature.

Does MPQ8623GD-Z support remote output voltage sensing?

No - it lacks dedicated remote sense pins (e.g., VSNS+/VSNS−). Output regulation relies solely on the FB pin connected to the local output node. For remote sensing, external circuitry (e.g., op-amp buffer) would be required, but this is not supported by the IC's internal architecture or datasheet recommendations.