Monolithic Power Systems Inc. MPQ8626GD-P

Overview

MPQ8626GD-P from Monolithic Power Systems is a fully integrated, synchronous step-down DC/DC converter delivering up to 6A output current with adjustable current limit, operating from 4V–16V input and supporting 0.6V–6V output. It features adaptive constant-on-time (COT) control, selectable 600/1100/2000kHz switching frequency, and integrated 22.6mΩ/8.1mΩ MOSFETs for high efficiency in telecom PoL and server power rails.

For engineers reviewing the MPQ8626GD-P datasheet, MPQ8626GD-P pinout, MPQ8626GD-P application, or MPQ8626GD-P equivalent, key selection criteria include its programmable current limit via CS pin, PGOOD open-drain status signaling, TRK/REF-based voltage tracking, pre-bias start-up capability, and QFN-14 (2mm×3mm) thermal performance with θJB = 6.8°C/W.

Technical Context

The MPQ8626GD-P implements an internally compensated adaptive COT control architecture that maintains stable regulation across wide VIN/VOUT ranges without external loop compensation. Its valley-current sensing via CS pin enables cycle-by-cycle over-current protection with programmable trip thresholds (e.g., 6A–8A), while internal ramp generation ensures stability with zero-ESR ceramic output capacitors.

It supports dual light-load modes-forced CCM and pulse-skip-selected via MODE pin resistor configuration, and integrates a 3V LDO (VCC) for gate drive, PGOOD comparator with 1ms delay, and OVP/UVP/OTP/UVLO protections with non-latching fault recovery. The TRK/REF pin enables precise output voltage tracking or external reference injection with 0.3V–1.4V analog input range.

Key Specifications

Pinout & Package

MPQ8626GD-P is housed in a thermally enhanced QFN-14 package (2mm × 3mm, 0.5mm pitch) with exposed thermal pad (PGND-connected) for low-junction-to-board thermal resistance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with RTQ2132BGQW and TPS546B24A, MPQ8626GD-P delivers optimal balance of analog flexibility (TRK/REF, MODE-selectable fSW), compact QFN-14 footprint, and robust protection set-making it ideal for cost-sensitive, space-constrained analog PoL designs where digital control is unnecessary.

Availability

MPQ8626GD-P is available at Aetrix Electronics and suitable for telecom infrastructure, cloud storage SSDs, and high-end GPU power delivery requiring stable component supply, consistent parametric performance, and long-term production continuity.

Supply support for MPQ8626GD-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The MPQ8626GD-P belongs to MPS's MPQ high-efficiency synchronous buck converter product line, engineered specifically for demanding point-of-load applications in telecom, enterprise computing, and graphics subsystems where small size, fast transient response, and thermal resilience are critical.

FAQ

What is the minimum recommended input capacitance for MPQ8626GD-P?

MPQ8626GD-P requires ≥10µF of low-ESR ceramic input capacitance placed directly at the VIN and PGND pins. A combination of one 10µF X7R 0805 and two 1µF X7R 0402 capacitors is recommended to suppress high-frequency noise and handle peak inrush currents during startup.

How does the TRK/REF pin function during pre-bias start-up?

During pre-bias start-up, the TRK/REF capacitor charges only after the output voltage (VFB) rises above the initial TRK/REF voltage. If VFB is pre-biased, the LS-FET pulses briefly to charge BST without discharging VOUT, ensuring monotonic rise once TRK/REF exceeds 600mV-the minimum required for regulation initiation.

Can MPQ8626GD-P operate without an external bootstrap capacitor?

No. A 0.1µF X7R ceramic capacitor must be placed between BST and SW pins. This capacitor supplies the floating gate drive voltage for the high-side MOSFET; omission causes immediate failure to regulate due to insufficient HS-FET turn-on voltage.

What happens to PGOOD when input voltage collapses below UVLO threshold?

When VIN drops below 2.25V (rising threshold), PGOOD is actively clamped to ~0.7V regardless of external pull-up voltage. This low-level assertion persists until VIN recovers above 2.55V and a new soft-start sequence completes, preventing false "power good" assertions during brown-out conditions.

Is the current limit threshold affected by temperature?

Yes. The CS-to-current gain (GCS = 40µA/A) and OCP threshold (1.2V nominal) exhibit ±10% variation over −40°C to +125°C. For designs requiring tight current limit accuracy across temperature, use the RCS values in Table 2 and verify at worst-case junction temperature during qualification.

Does MPQ8626GD-P support forced continuous conduction mode at light load?

Yes. Connecting MODE to AGND with a 30.1kΩ resistor configures forced CCM operation at 1100kHz, eliminating light-load frequency variation and output voltage ripple modulation-critical for noise-sensitive analog or RF circuitry powered from this rail.

What is the maximum allowable voltage on the CS pin during normal operation?

The CS pin must remain ≤1.25V during normal operation. Exceeding this risks erroneous OCP triggering or damage. The internal OCP comparator trips at 1.2V ±50mV, and the absolute maximum rating for CS is 4.3V-so external filtering or clamping is advised if layout introduces noise coupling.