Monolithic Power Systems Inc. MPQ8632DGLE-6-P

Overview

MPQ8632DGLE-6-P from Monolithic Power Systems is a fully integrated, high-frequency synchronous step-down converter delivering up to 6A output current with 2.5V–18V input range (with external 5V bias) or 4.5V–18V (with internal bias), 0.611V–13V adjustable output, and proprietary adaptive Constant-On-Time (COT) control for ultrafast transient response in telecom power rails and server point-of-load applications.

For engineers reviewing the MPQ8632DGLE-6-P datasheet, MPQ8632DGLE-6-P pinout, MPQ8632DGLE-6-P application, or MPQ8632DGLE-6-P equivalent, key selection criteria include its 28 mΩ high-side/15.8 mΩ low-side MOSFET R_DS(ON), programmable 200 kHz–1 MHz switching frequency via FREQ pin, 0.5% reference voltage accuracy over –40°C to +125°C, non-latch OCP/OVP, and soft-start/shut-down timing control.

Technical Context

The MPQ8632DGLE-6-P implements adaptive COT control without an external oscillator, using VIN feed-forward through the FREQ pin to maintain near-constant switching frequency across input voltage variation. Its dual current-limit protection includes valley-current limit (6.5–8.5 A) and negative-current limit (–4 to –1 A) for robust overload handling.

It integrates a 4.8V internal LDO (VCC), bootstrap gate driver (BST), open-drain power-good (PG) with 2.5 ms delay and 90%/120% V_FB thresholds, and pre-bias startup capability - enabling reliable operation into pre-charged outputs without reverse current or voltage overshoot.

Key Specifications

Pinout & Package

MPQ8632DGLE-6-P is housed in a thermally enhanced 3 mm × 4 mm QFN package with exposed thermal pad (PGND-connected), supporting high-density PCB layouts and efficient heat dissipation in space-constrained systems.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MPQ8632-6, this EOL-marked MPQ8632DGLE-6-P shares identical performance and layout compatibility but lacks future supply assurance; versus TPS546B24A, it trades digital configurability for lower BOM cost, smaller size, and zero-firmware implementation.

Availability

MPQ8632DGLE-6-P is available at Aetrix Electronics and suitable for telecom infrastructure, server power delivery, industrial control, and networking equipment requiring stable component supply during legacy design support and transition phases.

Supply support for MPQ8632DGLE-6-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with a focus on energy-efficient DC/DC conversion, motor drivers, and LED lighting solutions.

The MPQ8632D series belongs to MPS's high-current synchronous buck converter product line, engineered for compact, high-efficiency point-of-load regulation in demanding communications and computing applications.

FAQ

What is the recommended minimum SS capacitor value for MPQ8632DGLE-6-P?

The minimum SS capacitor is 4.7 nF when output capacitance exceeds 330 µF. This prevents current-limit triggering during soft start by ensuring sufficient ramp time. The soft-start time is half the soft-shutdown time, both determined by ISS = 20 µA charge and ISD = 10 µA discharge currents into the SS capacitor.

Can MPQ8632DGLE-6-P operate with a 3.3 V input supply?

Yes - with external 5 V bias applied to VCC, the input voltage range extends down to 2.5 V. Without external bias, the minimum input is 4.5 V due to internal LDO requirements. External bias disables the internal VCC LDO and allows operation from 3.3 V input rails.

How does the power-good (PG) signal behave during startup and fault conditions?

PG remains low until FB reaches 90% of V_REF, then asserts high after a fixed 2.5 ms delay. It pulls low if FB drops below 85% V_REF or exceeds 120% V_REF, or if VCC fails - even with an external pull-up. PG is open-drain and requires a 100 kΩ pull-up to ≤5.5 V.

What is the purpose of the FREQ pin, and how is switching frequency set?

The FREQ pin sets the one-shot ON-time via a resistor to IN, enabling feed-forward stabilization of switching frequency across input voltage changes. Frequency ranges from 200 kHz to 1 MHz and is calculated using F_SW(kHz) ≈ 10⁶ / [6.1 × R_FREQ(kΩ) × (V_IN − 0.4 V)]. No external oscillator is needed.

Does MPQ8632DGLE-6-P support pre-biased output startup?

Yes - it detects pre-bias on the FB pin and holds both high-side and low-side MOSFETs off until the SS capacitor voltage exceeds the pre-charged output voltage. This prevents reverse current flow and ensures monotonic startup without output collapse or overshoot.

What thermal considerations apply to the QFN (3×4 mm) package?

The package has θ_JA = 46°C/W and θ_JC = 9°C/W on a 4-layer JEDEC PCB. For 6 A continuous operation, ensure the exposed thermal pad is soldered to a solid PGND plane with ≥4 thermal vias. Maximum junction temperature is 150°C; thermal shutdown activates at 150°C with 25°C hysteresis.