Texas Instruments MSP430FR5729IDAR
- Part No.:
- MSP430FR5729IDAR
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 38-TSSOP (0.240", 6.10mm Width)
- Datasheet:
-
MSP430FR5729IDAR.pdf
- Description:
- IC MCU 16BIT 16KB FRAM 38TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:8,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MSP430FR5729IDAR from Texas Instruments is a 16-bit ultra-low-power FRAM microcontroller featuring 16KB nonvolatile FRAM, 1KB RAM, 10-bit ADC with 12 external channels, 16-channel analog comparator, and dual eUSCI modules supporting UART/IrDA/SPI/I²C. It operates from 2 V to 3.6 V across –40°C to 85°C and targets battery-powered sensor nodes and data loggers requiring fast write endurance and RTC-based wake-up.
For engineers reviewing the MSP430FR5729IDAR datasheet, MSP430FR5729IDAR pinout, MSP430FR5729IDAR application, or MSP430FR5729IDAR equivalent, key selection criteria include FRAM write cycle endurance (10¹⁵), real-time clock with calendar mode, low-power LPM3.5 current (1.5 µA), and TSSOP-38 package compatibility with legacy MSP430 designs.
Technical Context
The MSP430FR5729IDAR implements a 16-bit CPUXV2 core with hardware multiplier and three-channel DMA, enabling efficient signal processing in active mode (81.4 µA/MHz). Its memory subsystem integrates FRAM with built-in ECC and MPU for code/data/storage unification-eliminating separate flash/EEPROM partitions.
Peripherals include five 16-bit timers (three Timer_A and three Timer_B instances), RTC with alarm/calendar, and dual enhanced USCI modules: eUSCI_A0/A1 support UART/IrDA/SPI, while eUSCI_B0 supports I²C and SPI. The analog subsystem features programmable hysteresis on all 16 comparator inputs and internal reference generation for ADC and comparator operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 16-bit RISC CPUXV2 with 32-bit hardware multiplier and three-channel DMA |
| Nonvolatile Memory | 16KB FRAM with 10¹⁵ write cycles, 125 ns/word write speed, ECC and MPU protection |
| ADC | 10-bit SAR ADC with 12 external + 2 internal channels, 200 ksps at 100 µA |
| Comparator | 16-channel analog comparator with programmable hysteresis and internal voltage reference |
| Timers | Five 16-bit timers: two Timer_A (3 CC each) and three Timer_B (3 CC each) |
| eUSCI Peripherals | eUSCI_A0/A1: UART/IrDA/SPI; eUSCI_B0: I²C/SPI; hardware UART bootloader (BSL) |
| Low-Power Modes | LPM3.5 (RTC + crystal): 1.5 µA; LPM4.5 (shutdown): 0.32 µA; Active: 81.4 µA/MHz |
Pinout & Package
TSSOP-38 package (body size 12.5 mm × 6.2 mm) with exposed thermal pad recommended to be connected to DVSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF- | Multi-function I/O | RTC calibration output, ADC channel A0 input, comparator CD0 input, DMA trigger source |
| P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+ | Multi-function I/O | ADC reference input (VeREF+), comparator output, TA0/TA1 clock source |
| P1.4/TB0.1/UCA0STE/A4*/CD4 | Multi-function I/O | eUSCI_A0 SPI slave transmit enable, ADC channel A4 input, comparator CD4 input |
| P1.5/TB0.2/UCA0CLK/A5*/CD5 | Multi-function I/O | eUSCI_A0 SPI clock (master out/slave in), ADC channel A5 input, comparator CD5 input |
| P2.5/TB0.0/UCA1TXD/UCA1SIMO | Multi-function I/O | eUSCI_A1 UART transmit / SPI master-out-slave-in, TB0 capture/compare channel 0 |
| P2.6/TB1.0/UCA1RXD/UCA1SOMI | Multi-function I/O | eUSCI_A1 UART receive / SPI master-in-slave-out, TB1 capture/compare channel 0 |
| RST/NMI/SBWTDIO | System control | Reset input, non-maskable interrupt, Spy-Bi-Wire debug data I/O |
| TEST/SBWTCK | Debug interface | Spy-Bi-Wire clock input for programming and debugging |
| PJ.4/XIN & PJ.5/XOUT | Clock system | LFXT crystal oscillator connections for 32-kHz real-time clock operation |
| DVCC / DVSS / AVCC / AVSS | Power domains | Digital supply (2–3.6 V), analog supply (separate filtering required), core voltage regulation via integrated LDO |
Key Features
| Feature | Design Value |
|---|---|
| FRAM memory architecture | Unifies program, data, and storage in single 16KB nonvolatile memory with zero-wait-state writes and no erase cycles |
| Real-time clock with calendar | Hardware RTC with alarm, calendar, and crystal-accurate timekeeping in LPM3.5 (1.5 µA) |
| Ultra-low-power analog subsystem | 10-bit ADC consumes only 100 µA at 200 ksps; comparator supports hysteresis and internal reference without external components |
| Enhanced serial interfaces | Dual eUSCI_A modules support automatic baud-rate detection and IrDA encoding; eUSCI_B0 enables multi-address I²C slave operation |
| Integrated power management | Fully integrated LDO, supply voltage supervisor (SVS), zero-power brownout detection, and serial onboard programming without external voltage |
Applications
| Smart Metering Endpoint | Wireless Sensor Node |
|---|---|
Use Scenario: Battery-powered electricity/water meter collecting consumption data hourly and transmitting via LPWAN. IC Role / Device Role / Timing Role: Primary MCU managing ADC sampling, RTC-triggered wake-up, FRAM-based data logging, and UART/I²C communication with metrology ICs and transceivers. Use Value: 10¹⁵ FRAM write cycles enable decade-long logging without wear leveling; LPM3.5 RTC mode draws only 1.5 µA for precise timekeeping between reads. | Use Scenario: Industrial temperature/humidity node deployed in remote locations with 10-year battery life requirement. IC Role / Device Role / Timing Role: System controller acquiring analog sensor signals, performing local threshold detection via comparator, and waking periodically via RTC alarm to transmit data. Use Value: Comparator with programmable hysteresis reduces false triggers; FRAM allows instant data save on interrupt without delay or flash wear concerns. |
| Home Automation Hub | Asset Tracking Tag |
Use Scenario: Low-cost gateway aggregating Zigbee/Z-Wave sensor data and bridging to Wi-Fi/Ethernet. IC Role / Device Role / Timing Role: Peripheral manager interfacing with multiple sensors and radios via I²C, SPI, and UART; handles protocol translation and local decision logic. Use Value: Dual eUSCI_A and eUSCI_B enable concurrent UART (radio) and I²C (sensor) traffic without software overhead; 16KB FRAM stores firmware updates and configuration securely. | Use Scenario: GPS-enabled logistics tag reporting location every 6 hours using cellular or NB-IoT. IC Role / Device Role / Timing Role: Power-optimized host controlling GPS module, cellular modem, and motion-detecting accelerometer via GPIO and UART. Use Value: LPM4.5 shutdown mode draws just 0.32 µA; hardware BSL enables field firmware updates over UART without dedicated programmer. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power mixed-signal microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MSP430FR5969IPM | 128KB FRAM, 8KB RAM, integrated AES accelerator, higher pin count (64-pin NFBGA) | Better suited for secure firmware updates and larger algorithm buffers; requires PCB redesign | Select when cryptographic security or >16KB code space is required |
| MSP430F5529IPN | 128KB flash, 8KB RAM, no FRAM, higher active current (170 µA/MHz), same TSSOP-40 footprint | Lacks FRAM endurance and instant-write capability; compatible with existing flash-based toolchains | Select when cost-sensitive designs prioritize flash density over write endurance and ultra-low LPM3.5 current |
Compared with MSP430FR5969IPM, the MSP430FR5729IDAR offers lower system cost and smaller TSSOP-38 footprint but less memory and no crypto engine; versus MSP430F5529IPN, it delivers superior write endurance and 57% lower RTC-active current, though with reduced flash-equivalent capacity.
Availability
MSP430FR5729IDAR is available at Aetrix Electronics and suitable for smart metering endpoints, wireless sensor nodes, home automation hubs, and asset tracking tags requiring stable component supply, long-term manufacturability, and TI's industrial-grade qualification.
Supply support for MSP430FR5729IDAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and consumer markets.
The MSP430FR57xx family was designed specifically for ultra-low-power sensing and system management in building automation, smart grid infrastructure, and industrial monitoring-leveraging FRAM to eliminate flash write limitations in data-logging and event-driven applications.
FAQ
What is the maximum operating frequency of the MSP430FR5729IDAR?
The MSP430FR5729IDAR supports a maximum system clock frequency of 8 MHz, achieved via its factory-trimmed DCO oscillator or external HFXT crystal. This frequency is fully supported across the entire specified operating voltage range (2 V to 3.6 V) and temperature range (–40°C to 85°C), enabling deterministic real-time performance in timing-critical sensor acquisition and control loops.
Does the MSP430FR5729IDAR include hardware encryption capabilities?
No, the MSP430FR5729IDAR does not include dedicated hardware encryption accelerators such as AES or SHA engines. Its security model relies on software-based implementations and the Memory Protection Unit (MPU) for code/data isolation. For applications requiring hardware-accelerated cryptography, consider the MSP430FR5969IPM, which integrates an AES-128 accelerator and is part of the same FRAM MCU family.
How many I²C interfaces does the MSP430FR5729IDAR support?
The MSP430FR5729IDAR supports one hardware I²C interface via eUSCI_B0, capable of multi-slave addressing and standard/fast-mode operation up to 400 kHz. It does not include a second independent I²C peripheral; additional I²C buses must be implemented in software using GPIO bit-banging or shared with other eUSCI functions.
What is the purpose of the VeREF+ and VeREF- pins on the MSP430FR5729IDAR?
The VeREF+ (P1.1) and VeREF- (P1.0) pins on the MSP430FR5729IDAR provide differential external reference inputs for the 10-bit ADC and analog comparator. VeREF+ accepts a positive reference voltage up to AVCC, while VeREF- sets the negative reference level-enabling ratiometric or precision measurements independent of AVCC fluctuations. Both pins also serve dual roles as general-purpose I/O and ADC channel inputs.
Can the MSP430FR5729IDAR operate from a single 1.8-V supply?
No, the MSP430FR5729IDAR requires a minimum supply voltage of 2.0 V per its recommended operating conditions. Operation below 2.0 V is outside specification and may result in unstable FRAM retention, incorrect ADC conversion, or failure of the integrated LDO regulator. For sub-2-V operation, consider the MSP430FR2355 or MSP430FR2476, which support down to 1.8 V.
MSP430FR5729IDAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 38-TSSOP (0.240", 6.10mm Width)
- Series:
- MSP430™ FRAM
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- MSP430 CPUXV2
- Core Size:
- 16-Bit
- Speed:
- 8MHz
- Connectivity:
- I2C, IrDA, LINbus, SCI, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 30
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FRAM
- EEPROM Size:
- -
- RAM Size:
- 1K x 8
- Voltage - Supply (Vcc/Vdd):
- 2V ~ 3.6V
- Data Converters:
- A/D 14x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MSP430FR5729IDAR FAQ
1.How can I place an order for MSP430FR5729IDAR through Aetrix?
Please submit a Request for Quotation (RFQ) for MSP430FR5729IDAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MSP430FR5729IDAR reliable?
The price and inventory of MSP430FR5729IDAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MSP430FR5729IDAR is usually 5 days.
3.What payment methods are accepted for MSP430FR5729IDAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MSP430FR5729IDAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MSP430FR5729IDAR?
MSP430FR5729IDAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MSP430FR5729IDAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MSP430FR5729IDAR?
For technical support, including MSP430FR5729IDAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MSP430FR5729IDAR requirements.
6.How does Aetrix verify that MSP430FR5729IDAR is sourced from the original manufacturer or authorized distributors?
All MSP430FR5729IDAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MSP430FR5729IDAR meets industry standards.
7.What is the process for return or replacement of MSP430FR5729IDAR?
All MSP430FR5729IDAR units undergo pre-shipment inspection (PSI). If there is an issue with MSP430FR5729IDAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MSP430FR5729IDAR part is unused and in its original packaging.
Return procedure for MSP430FR5729IDAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MSP430FR5729IDAR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

