Texas Instruments MSP430FR5959IDAR
- Part No.:
- MSP430FR5959IDAR
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 38-TSSOP (0.240", 6.10mm Width)
- Datasheet:
-
MSP430FR5959IDAR.pdf
- Description:
- IC MCU 16BIT 64KB FRAM 38TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,882
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MSP430FR5959IDAR from Texas Instruments is a 16-bit ultra-low-power FRAM microcontroller with 64KB nonvolatile memory, 2KB RAM, 12-bit ADC (14 external + 2 internal channels), RTC with calendar/alarm, and dual eUSCI modules supporting UART, SPI, and I²C. It operates from 1.8 V to 3.6 V and targets battery-powered sensor nodes and data loggers.
For engineers reviewing the MSP430FR5959IDAR datasheet, MSP430FR5959IDAR pinout, MSP430FR5959IDAR application, or MSP430FR5959IDAR equivalent, key selection criteria include FRAM endurance (10¹⁵ writes), LPM3.5 current (0.25 µA typical), HFXT oscillator support, TSSOP-38 package compatibility, and integrated AES-256 encryption for secure firmware updates.
Technical Context
The MSP430FR5959IDAR implements the CPUXV2 16-bit RISC core with 16 registers and executes instructions at up to 16 MHz using a factory-trimmed DCO or external HFXT (up to 24 MHz). Its memory subsystem integrates 64KB FRAM as unified program/data/storage space, eliminating separate flash/EEPROM partitions and enabling atomic writes without erase cycles.
Peripherals include five 16-bit timers (TA0–TA3, TB0), a 32-bit hardware multiplier, 3-channel DMA, 16-channel analog comparator, and eUSCI_A0/eUSCI_B0 supporting UART (with auto-baud detection), IrDA, SPI, and I²C. The device supports HFXT only - no LFXT or RTC_B functionality - per its variant specification in the family datasheet.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | CPUXV2 16-bit RISC, up to 16 MHz clock speed with DCO or HFXT |
| FRAM Capacity | 64KB unified nonvolatile memory enabling instant write, 10¹⁵ endurance, no erase required |
| ADC Resolution | 12-bit SAR ADC with 14 external + 2 internal input channels and integrated reference |
| Low-Power Mode LPM3.5 | 0.25 µA typical current draw with RTC active - enables calendar-based wake-up in battery systems |
| eUSCI Peripherals | eUSCI_A0 (UART/IrDA/SPI) and eUSCI_B0 (I²C/SPI) - dual independent serial interfaces |
| Crypto Engine | AES-256 coprocessor with dedicated hardware acceleration for secure boot and OTA updates |
| Supply Voltage Range | 1.8 V to 3.6 V - supports direct Li-ion/Li-poly battery operation without regulator overhead |
Pinout & Package
TSSOP-38 package (12.5 mm × 6.2 mm), thermally enhanced with exposed pad connected to DVSS. Pinout validated per Figure 4-5 and Table 4-1 of SLAS704G Rev. G.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF- | GPIO / Timer A0 CCR1 / ADC A0 / Comparator C0 / Ref- | Multi-function pin supporting analog sensing, timing capture, and DMA trigger - critical for low-latency sensor sampling |
| P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | GPIO / Timer A0 CCR2 / TA1 clock / Comparator out / ADC A1 / Ref+ | Enables synchronized timer/ADC/comparator operation - used for threshold-triggered wake-up and reference calibration |
| P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | GPIO / Timer B0 CCR6 / eUSCI_A0 TX / SPI master out / TB0 clock / ACLK output | Primary UART transmit and SPI master interface; ACLK output allows system-wide clock distribution to peripherals |
| P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 | GPIO / Timer B0 CCR0 / eUSCI_A0 RX / SPI master in / TB0 CCR0 | Dual-role UART receive and timer capture - supports time-stamped command parsing and pulse-width measurement |
| RST/NMI/SBWTDIO | Reset / Non-maskable interrupt / Spy-Bi-Wire debug I/O | Single-pin debug interface enables in-circuit programming and real-time trace without dedicated JTAG pins |
| DVCC / DVSS / AVCC / AVSS | Digital power / Digital ground / Analog power / Analog ground | Separate analog/digital supply domains reduce noise coupling - essential for 12-bit ADC accuracy |
Key Features
| Feature | Design Value |
|---|---|
| Ferroelectric RAM (FRAM) | 64KB unified memory enables zero-wait-state code execution, instant nonvolatile logging, and 10¹⁵ write endurance - eliminates flash wear-out in data-intensive applications |
| Ultra-Low-Power Operation | LPM3.5 draws only 0.25 µA with RTC active - extends coin-cell battery life to >10 years in periodic-sampling sensor nodes |
| Hardware AES-256 Engine | Dedicated crypto accelerator offloads encryption/decryption from CPU - reduces firmware update latency and preserves real-time responsiveness |
| Capacitive Touch I/O | All GPIO pins support capacitive touch sensing without external components - enables cost-effective human interface on compact PCBs |
| Integrated 12-bit ADC | 14 external analog inputs with programmable sample-and-hold and internal reference - supports multi-sensor monitoring with <1 LSB INL |
Applications
| Smart Utility Metering | Energy-Harvesting Sensor Node |
|---|---|
Use Scenario: Gas/water meter with hourly pulse counting, temperature compensation, and tamper detection. IC Role / Device Role / Timing Role: Main controller executing metrology algorithms, managing FRAM-based event logs, and driving LCD via GPIO. Use Value: FRAM enables reliable timestamped tamper-event storage across 10+ years; LPM3.5 current ensures >15-year battery life. | Use Scenario: Wireless environmental sensor powered by solar cell + supercapacitor, transmitting temperature/humidity every 5 minutes. IC Role / Device Role / Timing Role: System-on-chip managing energy harvesting, sensor acquisition, AES-encrypted BLE packet generation, and RTC-driven wake-up. Use Value: HFXT stability ensures accurate timing for radio synchronization; FRAM withstands unlimited write cycles from intermittent power. |
| Wearable Health Monitor | Industrial Data Logger |
Use Scenario: ECG patch recording raw analog waveforms during activity, compressing and storing locally before upload. IC Role / Device Role / Timing Role: Real-time signal acquisition via 12-bit ADC, on-chip FFT using MPY32, and FRAM-based circular buffer management. Use Value: Unified FRAM eliminates copy overhead between RAM and flash - enables continuous 250 SPS waveform capture with zero dropouts. | Use Scenario: DIN-rail mounted logger capturing vibration, temperature, and voltage from rotating machinery every second for predictive maintenance. IC Role / Device Role / Timing Role: Time-synchronized multi-channel sampling using RTC alarm and DMA-triggered ADC sequences. Use Value: 64KB FRAM stores >1 million 12-bit samples; AES-256 secures firmware updates over industrial Ethernet. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MSP430FR5969IRHAT | 48-pin VQFN package; adds HFXT + LFXT oscillators and full RTC_B module with calendar/alarm | Supports dual-crystal timing and sub-second RTC resolution - required for precise time-of-use metering | Select when calendar-based scheduling, sub-second timekeeping, or crystal redundancy is mandatory |
| MSP430FR5958IDAR | 48KB FRAM, same TSSOP-38 package and peripheral set - differs only in memory size | Reduces BOM cost where 48KB suffices for firmware + logs; identical power/performance envelope | Select for cost-sensitive designs with predictable memory usage below 48KB |
Compared with MSP430FR5969IRHAT, the MSP430FR5959IDAR trades RTC_B and LFXT support for identical HFXT performance in a smaller footprint; versus MSP430FR5958IDAR, it delivers 16KB additional FRAM for extended data retention without changing layout or firmware architecture.
Availability
MSP430FR5959IDAR is available at Aetrix Electronics and suitable for smart utility metering, energy-harvesting sensor nodes, and wearable health monitors requiring stable component supply and long-term production continuity.
Supply support for MSP430FR5959IDAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and consumer markets.
The MSP430 ULP FRAM portfolio targets energy-constrained applications such as battery-powered sensors, portable medical devices, and smart meters - emphasizing FRAM endurance, sub-µA sleep modes, and integrated analog peripherals.
FAQ
What is the maximum operating frequency of the MSP430FR5959IDAR?
The MSP430FR5959IDAR supports a maximum system clock frequency of 16 MHz using its factory-trimmed DCO or an external HFXT oscillator. The device's CPUXV2 core executes instructions at this rate with zero wait states, and all peripherals-including the 12-bit ADC and eUSCI modules-are fully functional at 16 MHz. This frequency enables real-time signal processing while maintaining ultra-low-power efficiency.
Does the MSP430FR5959IDAR support low-frequency crystal (LFXT) operation?
No, the MSP430FR5959IDAR does not support LFXT operation. As confirmed in the device comparison table and functional block diagram notes, MSP430FR595x variants are HFXT-only devices and exclude the LFXT oscillator, LFXIN/LFXOUT pins, and RTC_B module. The MSP430FR5959IDAR relies solely on DCO or HFXT (up to 24 MHz) for clocking, and its RTC functionality is limited to LPM3.5 domain operation using VLO or DCO-derived clocks.
How many analog input channels does the MSP430FR5959IDAR ADC support?
The MSP430FR5959IDAR integrates a 12-bit ADC12_B module supporting 14 external analog input channels (A0–A13) plus 2 internal channels (temperature sensor and VREF generator output). This configuration is explicitly documented in Table 3-1 and Section 4.2 of the SLAS704G datasheet. All 14 external channels are accessible on the TSSOP-38 package, enabling simultaneous multi-sensor monitoring without external multiplexing.
What debug interface does the MSP430FR5959IDAR use?
The MSP430FR5959IDAR uses the two-wire Spy-Bi-Wire (SBW) interface via the RST/NMI/SBWTDIO and TEST/SBWTCK pins. This interface provides full JTAG-equivalent functionality-including flash programming, real-time debugging, and EnergyTrace++ power profiling-using only two pins. SBW eliminates the need for a 4-pin JTAG header, reducing PCB footprint and simplifying test fixture design for high-volume manufacturing.
Is the MSP430FR5959IDAR pin-compatible with other MSP430FR59xx devices in TSSOP-38?
Yes, the MSP430FR5959IDAR is pin-compatible with MSP430FR5958IDAR and MSP430FR5957IDAR in the TSSOP-38 package. All three share identical pin assignments, electrical characteristics, and peripheral mappings per Figures 4-3 and 4-5 and Table 4-1 of SLAS704G. This allows direct substitution within the same hardware design when memory or feature scaling is required, without PCB revision.
MSP430FR5959IDAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 38-TSSOP (0.240", 6.10mm Width)
- Series:
- MSP430™ FRAM
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- MSP430 CPUXV2
- Core Size:
- 16-Bit
- Speed:
- 16MHz
- Connectivity:
- I2C, IrDA, SCI, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 31
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FRAM
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 12x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MSP430FR5959IDAR FAQ
1.How can I place an order for MSP430FR5959IDAR through Aetrix?
Please submit a Request for Quotation (RFQ) for MSP430FR5959IDAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MSP430FR5959IDAR reliable?
The price and inventory of MSP430FR5959IDAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MSP430FR5959IDAR is usually 5 days.
3.What payment methods are accepted for MSP430FR5959IDAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MSP430FR5959IDAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MSP430FR5959IDAR?
MSP430FR5959IDAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MSP430FR5959IDAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MSP430FR5959IDAR?
For technical support, including MSP430FR5959IDAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MSP430FR5959IDAR requirements.
6.How does Aetrix verify that MSP430FR5959IDAR is sourced from the original manufacturer or authorized distributors?
All MSP430FR5959IDAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MSP430FR5959IDAR meets industry standards.
7.What is the process for return or replacement of MSP430FR5959IDAR?
All MSP430FR5959IDAR units undergo pre-shipment inspection (PSI). If there is an issue with MSP430FR5959IDAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MSP430FR5959IDAR part is unused and in its original packaging.
Return procedure for MSP430FR5959IDAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MSP430FR5959IDAR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

