Texas Instruments MSP430G2955IRHA40T
- Part No.:
- MSP430G2955IRHA40T
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
MSP430G2955IRHA40T.pdf
- Description:
- IC MCU 16BIT 56KB FLASH 40VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MSP430G2955IRHA40T from Texas Instruments is a 16-bit ultra-low-power mixed-signal microcontroller featuring 56 kB flash, 4 kB RAM, dual 16-bit Timer_A modules (TA0/TA1), one 16-bit Timer_B (TB0), 12-channel 10-bit ADC with internal reference and autoscan, USCI_A0 (UART/LIN/IrDA/SPI) and USCI_B0 (SPI/I²C), and up to 32 touch-sense-capable I/O pins in a 40-pin QFN package. It targets battery-powered sensor nodes and portable measurement systems requiring sub-1µs wake-up and <0.1 µA off-mode retention.
For engineers reviewing the MSP430G2955IRHA40T datasheet, MSP430G2955IRHA40T pinout, MSP430G2955IRHA40T application, or MSP430G2955IRHA40T equivalent, key selection criteria include its 56 kB flash capacity, 12-channel ADC with VREF+/VREF− inputs, QFN-40 pin mapping for high-density PCB layout, and support for LIN bus auto-baudrate detection in UART mode.
Technical Context
The MSP430G2955IRHA40T implements a 16-bit RISC CPU with 62.5-ns instruction cycle time, constant generators, and seven addressing modes. Its clock system integrates DCO (calibrated up to 16 MHz), 32-kHz crystal support, and internal LF oscillator - enabling five low-power modes including LPM4 with 0.1 µA retention.
Peripherals are memory-mapped and accessible via all instructions. The USCI_A0 module supports enhanced UART with LIN auto-baudrate detection and IrDA encoding/decoding; USCI_B0 provides full-duplex SPI and I²C master/slave operation. The on-chip comparator (COMP_A+) supports slope A/D conversion and analog signal thresholding.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 16-bit RISC CPU with 62.5-ns instruction cycle; register-based execution enables deterministic timing for real-time control loops. |
| Flash / RAM | 56 kB flash (main memory) + 256 B information memory; 4 kB RAM (2 kB extended + 2 kB mirrored); supports in-system programming via Spy-Bi-Wire. |
| ADC10 | 10-bit, 200-ksps SAR ADC with 12 input channels, internal 1.5 V/2.5 V reference, sample-and-hold, and autoscan mode for sequential sensor polling. |
| Timers | Two 16-bit Timer_A (TA0/TA1) with three capture/compare registers each; one 16-bit Timer_B (TB0) with three capture/compare registers; all support PWM, interval timing, and interrupt generation. |
| USCI Peripherals | USCI_A0: UART (LIN auto-baudrate), IrDA encoder/decoder, synchronous SPI; USCI_B0: SPI and I²C master/slave - enabling dual-protocol communication without external transceivers. |
| Power Modes | Active mode: 250 µA @ 1 MHz, 2.2 V; Standby: 0.7 µA; Off mode (RAM retention): 0.1 µA; wake-up from standby in <1 µs via DCO stabilization. |
| I/O Capability | Up to 32 GPIO pins with individually configurable pullup/pulldown resistors, edge-selectable interrupts (P1/P2), and integrated capacitive touch sensing oscillator enable bits. |
Pinout & Package
Package: 40-pin QFN (RHA), 6 mm × 6 mm, 0.5 mm pitch, exposed thermal pad connected to DVSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 / TEST/SBWTCK | Spy-Bi-Wire test clock input | Enables in-circuit debugging and flash programming using two-wire interface; no external voltage required. |
| 2 / DVCC | Digital supply voltage | 1.8–3.6 V digital core power rail; decoupling capacitor placement critical for low-noise operation. |
| 3 / P2.5/TA1.0/ROSC | Timer_A1 capture/compare input / DCO resistor terminal | Configurable as CCI0B input for TA1 or connection point for external resistor to calibrate DCO frequency. |
| 4 / XOUT/P2.7 | Crystal oscillator output / general-purpose I/O | Drives external 32-kHz crystal; must be configured as I/O before use as GPIO to avoid current leakage. |
| 5 / XIN/P2.6 | Crystal oscillator input / general-purpose I/O | Accepts 32-kHz crystal input; also usable as GPIO when crystal not enabled. |
| 6 / RST/NMI/SBWTDIO | Reset/non-maskable interrupt / Spy-Bi-Wire data I/O | Active-low reset input; doubles as bidirectional debug data line during programming. |
| 7 / P2.0/TA1CLK/ACLK/A0 | Timer_A1 clock / auxiliary clock output / ADC channel 0 | Provides ACLK source to peripherals; selectable as analog input A0 for ADC sampling. |
| 8 / P2.1/TA0INCLK/SMCLK/A1 | Timer_A0 clock input / sub-main clock output / ADC channel 1 | Routes SMCLK to timer or serves as ADC input A1; supports clock synchronization across modules. |
| 9 / P2.2/TA0.0/A2 | Timer_A0 capture/compare / ADC channel 2 | Supports CCI0A input for event capture or OUT0 output for PWM; dual-role reduces pin count for sensor interfaces. |
| 10 / P3.0/UCB0STE/UCA0CLK/A5 | USCI_B0 slave transmit enable / USCI_A0 clock / ADC channel 5 | Enables SPI slave mode or provides clock for UART; shared with ADC input simplifies multi-function routing. |
| 11 / P3.1/UCB0SIMO/UCB0SDA | USCI_B0 slave-in-master-out / I²C data line | Configurable for SPI data-in or I²C bidirectional SDA; requires software-controlled direction for I²C compliance. |
| 12 / P3.2/UCB0SOMI/UCB0SCL | USCI_B0 slave-out-master-in / I²C clock line | Functions as SPI MISO or I²C SCL; hardware automatically manages clock stretching in I²C slave mode. |
| 13 / P3.3/UCB0CLK/UCA0STE | USCI_B0 clock / USCI_A0 slave transmit enable | Shared clock resource for both USCI modules; UCA0STE enables hardware flow control in UART slave applications. |
| 14 / P4.0/TB0.0/CA0 | Timer_B0 capture/compare / Comparator_A+ input 0 | Enables synchronized PWM generation and analog threshold detection on same pin - ideal for closed-loop sensor control. |
| 15 / P4.1/TB0.1/CA1 | Timer_B0 capture/compare / Comparator_A+ input 1 | Supports dual-input analog comparison (e.g., window detection) while generating complementary PWM signals. |
| 16 / P4.2/TB0.2/CA2 | Timer_B0 capture/compare / Comparator_A+ input 2 | Extends analog monitoring capability to three independent thresholds with dedicated timer compare outputs. |
| 17 / P4.3/TB0.0/A12/CA3 | Timer_B0 capture/compare / ADC channel 12 / Comparator_A+ input 3 | Tri-function pin enables simultaneous analog acquisition, comparator triggering, and PWM modulation for energy harvesting control. |
| 18 / P4.4/TB0.1/A13/CA4 | Timer_B0 capture/compare / ADC channel 13 / Comparator_A+ input 4 | Allows correlated sampling of multiple analog sources with synchronized timer-based sequencing. |
| 19 / P4.5/TB0.2/A14/CA5 | Timer_B0 capture/compare / ADC channel 14 / Comparator_A+ input 5 | Supports 5-channel analog front-end with hardware autoscan and timer-triggered conversions. |
| 20 / P4.6/TB0OUTH/A15/CA6 | Timer_B0 output high-impedance / ADC channel 15 / Comparator_A+ input 6 | TB0OUTH disables all TB0 outputs simultaneously - essential for safe state transitions in motor control. |
| 21 / P4.7/TB0CLK/CA7 | Timer_B0 clock input / Comparator_A+ input 7 | Accepts external clock for precise timing control of TB0; CA7 extends comparator input to 8 channels. |
| 22 / DVSS | Digital ground reference | Primary digital return path; must be connected to QFN thermal pad for thermal and EMI performance. |
| 23 / AVCC | Analog supply voltage | 1.8–3.6 V analog rail; requires separate filtering from DVCC to maintain ADC SNR >60 dB. |
| 24 / AVSS | Analog ground reference | Isolated analog return; star-ground connection to DVSS at single point prevents noise coupling into ADC. |
| 25 / P3.4/UCA0TXD/UCA0SIMO | USCI_A0 transmit data / SPI master-out-slave-in | Drives UART TX or SPI MOSI; open-drain capable for wired-AND bus configurations. |
| 26 / P3.5/UCA0RXD/UCA0SOMI | USCI_A0 receive data / SPI master-in-slave-out | Accepts UART RX or SPI MISO; Schmitt-trigger input ensures robust noise immunity in industrial environments. |
| 27 / P3.6/TA1.1/A6 | Timer_A1 capture/compare / ADC channel 6 | Supports high-resolution timing of analog events (e.g., pulse width measurement) with direct ADC correlation. |
| 28 / P3.7/TA1.2/A7 | Timer_A1 capture/compare / ADC channel 7 | Enables dual-edge capture on A6/A7 for period/frequency measurement of unknown signals. |
| 29 / P2.4/TA0.2/A4/VREF+/VEREF+ | Timer_A0 capture/compare / ADC channel 4 / positive reference output/input | VREF+ can source 1.5 V or 2.5 V reference to external circuitry while serving as ADC input A4. |
| 30 / P2.3/TA0.1/A3/VREF−/VEREF− | Timer_A0 capture/compare / ADC channel 3 / negative reference output/input | VREF− provides precision ground reference for ratiometric sensor interfaces and differential ADC measurements. |
| 31 / P1.0/TA0CLK/ADC10CLK | Timer_A0 clock / ADC conversion clock | Shared clock source ensures synchronous sampling and timer-triggered conversions - critical for phase-sensitive measurements. |
| 32 / P1.1/TA0.0 | Timer_A0 capture/compare | Primary CCI0A input for edge-triggered event capture; also used for BSL serial programming (TX). |
| 33 / P1.2/TA0.1 | Timer_A0 capture/compare | CCI1A input for secondary event capture; supports dual-slope integration in analog front-end designs. |
| 34 / P1.3/TA0.2 | Timer_A0 capture/compare | CCI2A input for third event capture; enables three-phase motor commutation timing. |
| 35 / P1.4/SMCLK/TCK | Sub-main clock output / JTAG test clock | SMCLK output allows clock distribution to external peripherals; TCK enables boundary-scan testing. |
| 36 / P1.5/TA0.0/TMS | Timer_A0 compare output / JTAG test mode select | OUT0 drives external logic or LEDs; TMS controls JTAG state machine during debug sessions. |
| 37 / P1.6/TA0.1/TDI | Timer_A0 compare output / JTAG test data input | OUT1 provides PWM dimming control; TDI loads instruction/data during JTAG programming. |
| 38 / P1.7/TA0.2/TDO | Timer_A0 compare output / JTAG test data output | OUT2 enables three-level PWM; TDO streams debug data out during emulation. |
| 39 / DVCC | Digital supply voltage | Second DVCC pin for improved power delivery integrity in high-speed operation. |
| 40 / DVSS | Digital ground reference | Second DVSS pin for low-impedance return path; connects directly to QFN thermal pad. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power operation | 0.1 µA off-mode (RAM retention) and sub-1 µs wake-up enable multi-year battery life in wireless sensor nodes. |
| Integrated analog subsystem | 12-channel 10-bit ADC with internal reference, sample-and-hold, and autoscan eliminates need for external ADC and multiplexer. |
| Dual USCI modules | USCI_A0 (UART/LIN/IrDA/SPI) + USCI_B0 (SPI/I²C) provide protocol flexibility for interfacing with sensors, displays, and host controllers. |
| Touch-sense I/O capability | 32 GPIO pins with built-in oscillator enable bits support capacitive touch buttons/sliders without external components. |
| On-chip comparator | Comparator_A+ with 8 inputs enables analog threshold detection, window comparison, and slope A/D conversion for low-power wake-up triggers. |
| Programmable code protection | Security fuse prevents unauthorized flash readout; BSL password protection secures in-field firmware updates. |
Applications
| Wireless Sensor Node | Portable Medical Monitor |
|---|---|
|
Use Scenario: Battery-powered temperature/humidity sensor transmitting data via UART to BLE gateway. IC Role / Device Role / Timing Role: MSP430G2955IRHA40T performs analog sensing (ADC10), LIN-compatible UART communication, and ultra-low-power scheduling using Timer_A wake-up intervals. Use Value: 0.1 µA off-mode and 56 kB flash allow firmware-over-the-air updates and multi-year operation on coin-cell battery. |
Use Scenario: Wearable ECG patch acquiring biopotential signals and detecting arrhythmia events. IC Role / Device Role / Timing Role: MSP430G2955IRHA40T executes analog front-end conditioning (COMP_A+), 200-ksps ADC sampling, and real-time QRS detection using Timer_B PWM-triggered acquisition. Use Value: Integrated 12-channel ADC with VREF+/VREF− enables ratiometric measurement accuracy <±0.5% over temperature. |
| Industrial Control Panel | Smart Energy Meter |
|
Use Scenario: HMI panel with capacitive touch buttons, LED indicators, and RS-485 communication interface. IC Role / Device Role / Timing Role: MSP430G2955IRHA40T manages touch-sense I/O (32 pins), drives LEDs via Timer_A PWM, and handles UART-to-RS485 translation using USCI_A0. Use Value: Dual USCI modules eliminate external level shifters; touch-sense oscillator reduces BOM cost by 30% vs discrete solutions. |
Use Scenario: Electricity meter measuring voltage/current waveforms and calculating RMS/kWh values. IC Role / Device Role / Timing Role: MSP430G2955IRHA40T synchronizes 12-channel ADC sampling with zero-crossing detection (COMP_A+), computes harmonics via Timer_B-triggered FFT windows. Use Value: 16-bit timers with capture/compare registers enable precise 50/60 Hz cycle timing and harmonic analysis up to 25th order. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power mixed-signal microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MSP430G2855IRHA40 | 48 kB flash, 48 I/O pins, identical peripheral set except reduced flash size and I/O count. | Suitable for cost-sensitive designs with smaller firmware footprint and fewer sensor inputs. | Select when application firmware fits within 48 kB and ≤48 GPIOs are required; maintains same QFN-40 footprint and pinout. |
| MSP430G2755IRHA40 | 32 kB flash, 32 I/O pins, same architecture and peripherals but scaled-down memory and I/O resources. | Targeted at entry-level sensor nodes with basic analog acquisition and minimal communication requirements. | Choose for lowest-cost variant where 32 kB flash suffices and only 32 GPIOs are needed; fully compatible pinout and software stack. |
Compared with MSP430G2855IRHA40 and MSP430G2755IRHA40, the MSP430G2955IRHA40T provides 25% more flash than the G2855 and 75% more than the G2755, enabling complex sensor fusion algorithms and larger OTA update partitions while retaining identical power profiles and QFN-40 mechanical compatibility.
Availability
MSP430G2955IRHA40T is available at Aetrix Electronics and suitable for wireless sensor networks, portable medical devices, and industrial HMI panels requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for MSP430G2955IRHA40T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions for industrial, automotive, and consumer applications.
The MSP430G2xx family delivers ultra-low-power mixed-signal microcontrollers optimized for battery-operated sensor systems, portable instrumentation, and energy-constrained IoT endpoints - with emphasis on sub-1 µA sleep currents and fast wake-up response.
FAQ
What is the maximum operating frequency of the MSP430G2955IRHA40T?
The MSP430G2955IRHA40T supports an internal digitally controlled oscillator (DCO) calibrated up to 16 MHz, with additional clock sources including 32-kHz crystal (XIN/XOUT), internal very-low-power LF oscillator, and external digital clock input. The DCO calibration data is stored in information memory segment A, ensuring stable operation across voltage and temperature ranges. This allows the MSP430G2955IRHA40T to execute instructions at 16 MHz while maintaining ultra-low-power characteristics in active mode.
Does the MSP430G2955IRHA40T support LIN bus communication?
Yes, the MSP430G2955IRHA40T supports LIN bus communication through its USCI_A0 module, which includes enhanced UART functionality with automatic baudrate detection (LIN auto-baud). This feature enables reliable frame synchronization without requiring external LIN transceivers or precise timing references, making the MSP430G2955IRHA40T suitable for automotive body electronics and industrial control networks compliant with LIN 2.x specifications.
How many analog input channels does the ADC10 module support on the MSP430G2955IRHA40T?
The ADC10 module on the MSP430G2955IRHA40T supports 12 analog input channels (A0–A7, A12–A15), with additional dedicated pins for VREF+ and VREF− reference inputs. These channels are accessible via multiplexed GPIO pins including P2.0–P2.4, P3.6–P3.7, and P4.0–P4.7. The ADC10 also features internal 1.5 V/2.5 V reference generation, sample-and-hold, and hardware autoscan mode - allowing sequential conversion of all 12 channels without CPU intervention.
Can the MSP430G2955IRHA40T perform capacitive touch sensing without external components?
Yes, the MSP430G2955IRHA40T integrates capacitive touch-sense oscillator enable bits on up to 32 GPIO pins (P1–P4), allowing direct implementation of touch buttons, sliders, and wheels without external RC networks or dedicated touch controller ICs. Each pin's oscillator can be independently enabled and monitored via software, and the built-in comparator (COMP_A+) supports charge-transfer measurement techniques for robust noise immunity in noisy environments.
What debug interface does the MSP430G2955IRHA40T use?
The MSP430G2955IRHA40T uses the Spy-Bi-Wire (SBW) interface for debugging and programming, requiring only two pins: TEST/SBWTCK (pin 1) and RST/NMI/SBWTDIO (pin 6). This two-wire interface replaces traditional JTAG, reducing PCB footprint and connector complexity while supporting full-speed emulation, flash programming, and real-time variable inspection. The SBW interface operates at voltages from 1.8 V to 3.6 V and is compatible with TI's MSP-FET and LaunchPad development tools.
MSP430G2955IRHA40T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 40-VFQFN Exposed Pad
- Series:
- MSP430G2xx
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- MSP430 CPU16
- Core Size:
- 16-Bit
- Speed:
- 16MHz
- Connectivity:
- I2C, IrDA, LINbus, SCI, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 56KB (56K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 12x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
MSP430G2955IRHA40T FAQ
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5.How can I obtain technical support or documentation for MSP430G2955IRHA40T?
For technical support, including MSP430G2955IRHA40T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MSP430G2955IRHA40T requirements.
6.How does Aetrix verify that MSP430G2955IRHA40T is sourced from the original manufacturer or authorized distributors?
All MSP430G2955IRHA40T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MSP430G2955IRHA40T meets industry standards.
7.What is the process for return or replacement of MSP430G2955IRHA40T?
All MSP430G2955IRHA40T units undergo pre-shipment inspection (PSI). If there is an issue with MSP430G2955IRHA40T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MSP430G2955IRHA40T part is unused and in its original packaging.
Return procedure for MSP430G2955IRHA40T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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