NXP Semiconductors N74F153D,623
- Part No.:
- N74F153D,623
- Manufacturer:
- NXP Semiconductors
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
N74F153D,623.pdf
- Description:
- IC MULTIPLEXER 2 X 4:1 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:1,851
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
N74F153D,623 from Philips Semiconductors is a dual 4-line to 1-line TTL multiplexer in 16-pin SO package (SOT109-1), featuring non-inverting outputs, independent active-low enables (Ea, Eb), and common select inputs (S0, S1). It selects two parallel data bits from four input sources per section with 7.0 ns typical propagation delay, 12 mA typical supply current, and operates at 5.0 V ±10% over 0°C to +70°C - used in digital logic routing, address decoding, and bus multiplexing in industrial control systems.
For engineers reviewing the N74F153D,623 datasheet, N74F153D,623 pinout, N74F153D,623 application, or N74F153D,623 equivalent, key selection considerations include enable independence, common select architecture, TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2.0 V), output drive capability (IOL = 20 mA), and SO16 thermal and mounting constraints.
Technical Context
The N74F153D,623 implements two independent 4:1 multiplexer sections sharing S0/S1 select lines but with separate active-low enables (Ea, Eb), enabling asynchronous gating of each output (Ya, Yb). Each section routes one of four data inputs (I0n–I3n) to its output based on binary S0/S1 state, with outputs forced low when respective enable is high.
It adheres to FAST TTL logic family specifications: VCC = 4.5–5.5 V, input loading of 1.0 unit load (20 µA/0.6 mA), and output fan-out of 50/33 (high/low), supporting direct interfacing with standard 74F-series devices without level-shifting or buffering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74F FAST TTL - ensures compatibility with legacy 74F systems and higher speed than standard 74LS. |
| Propagation Delay (In→Yn) | 7.0 ns typical - enables reliable operation in 100 MHz+ clock domain edge sampling for control logic. |
| Supply Current (ICC) | 12 mA typical total - supports low-power board-level power budgeting in multi-device logic arrays. |
| Input Voltage Thresholds | VIL = 0.8 V, VIH = 2.0 V - guarantees noise margin >0.4 V under worst-case VCC = 4.5 V conditions. |
| Output Drive (IOL) | 20 mA low-level sink - directly drives LED indicators or interfaces with 74F inputs without external pull-ups. |
| Operating Temperature | 0°C to +70°C - validated for commercial-grade embedded controllers and instrumentation front-ends. |
| Package | SOT109-1 (SO16, 3.9 mm body width) - surface-mount compatible with standard reflow profiles and IPC-7351B land patterns. |
Pinout & Package
Package: 16-pin plastic small outline (SO), SOT109-1, 3.9 mm body width, gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Ea) | Port A Enable (active-low) | Asserting high disables Ya regardless of S0/S1 or I0a–I3a; allows independent strobing of section A. |
| 2 (S1) | Common Select Input MSB | Jointly controls both multiplexer sections; defines upper bit of 2-bit select code (S1S0). |
| 3 (I0a) | Port A Data Input 0 | Low-order data source for section A; selected when S1S0 = 00 and Ea = low. |
| 4 (I1a) | Port A Data Input 1 | Second data source for section A; selected when S1S0 = 01 and Ea = low. |
| 5 (I2a) | Port A Data Input 2 | Third data source for section A; selected when S1S0 = 10 and Ea = low. |
| 6 (I3a) | Port A Data Input 3 | High-order data source for section A; selected when S1S0 = 11 and Ea = low. |
| 7 (Ya) | Port A Output | Non-inverting output reflecting selected I0a–I3a; driven low when Ea = high. |
| 8 (GND) | Ground Reference | Primary return path for all internal logic and output currents; must be low-impedance connection. |
| 9 (Yb) | Port B Output | Non-inverting output reflecting selected I0b–I3b; driven low when Eb = high. |
| 10 (I0b) | Port B Data Input 0 | Low-order data source for section B; shares S0/S1 with section A but independent enable (Eb). |
| 11 (I1b) | Port B Data Input 1 | Second data source for section B; enables parallel dual-channel selection with shared address bus. |
| 12 (I2b) | Port B Data Input 2 | Third data source for section B; supports identical routing logic for two independent data paths. |
| 13 (I3b) | Port B Data Input 3 | High-order data source for section B; completes full 4-input coverage for second channel. |
| 14 (Eb) | Port B Enable (active-low) | Independent control of section B output; enables time-multiplexed or conditional routing of two data streams. |
| 15 (S0) | Common Select Input LSB | Jointly controls both sections; defines lower bit of 2-bit select code (S1S0). |
| 16 (VCC) | Positive Supply | +5.0 V ±10% supply rail; decoupling capacitor (100 nF ceramic) required within 10 mm of this pin. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enables (Ea, Eb) | Allows asynchronous gating of each 4:1 section without affecting the other - critical for interleaved data acquisition timing. |
| Common S0/S1 select lines | Reduces address/control bus width by 2 pins versus discrete multiplexers - simplifies PCB routing in space-constrained designs. |
| Non-inverting outputs (Ya, Yb) | Eliminates need for external inverters in feedback or monitoring paths where signal polarity must be preserved. |
| TTL-compatible input thresholds | Ensures interoperability with 74F, 74AS, and 74ALS families without level translation - lowers BOM count and design risk. |
| SO16 surface-mount package | Supports automated assembly and higher board density than DIP variants while maintaining identical logic functionality. |
Applications
| Industrial PLC I/O Expansion | Legacy Bus Address Decoding |
|---|---|
|
Use Scenario: Expanding digital input channels in programmable logic controllers using shared address lines and discrete enable signals. IC Role / Device Role / Timing Role: Dual-channel selector routing sensor status bits from four parallel input banks into two processor data lanes. Use Value: Reduces microcontroller GPIO usage by 4 pins versus single-channel muxes and eliminates software polling overhead via hardware-selectable inputs. |
Use Scenario: Decoding 16-bit memory-mapped peripheral addresses in 8086/80286-based industrial controllers. IC Role / Device Role / Timing Role: Selecting between four register banks (e.g., UART, timer, GPIO, ADC) using upper address bits A1–A0 as S1/S0. Use Value: Enables single-cycle peripheral access with no wait states, leveraging 7.0 ns propagation delay to meet 10 MHz bus timing. |
| Test Equipment Signal Routing | Digital Audio Channel Switching |
|
Use Scenario: Configurable signal path selection in automated test equipment for routing DUT outputs to multiple measurement instruments. IC Role / Device Role / Timing Role: Hardware-controlled switching between four analog-to-digital converter outputs using front-panel or GPIB commands. Use Value: Provides deterministic, glitch-free channel selection with independent enables - avoids metastability during instrument reconfiguration. |
Use Scenario: Selecting between four stereo audio sources (CD, tuner, tape, aux) in consumer AV receivers with discrete mute control. IC Role / Device Role / Timing Role: Routing left/right channel pairs through separate N74F153D,623 sections, each gated by source-specific enable. Use Value: Delivers zero-crossing mute capability via synchronized enable assertion, preventing audible pop during source switching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4:1 multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74F153N | DIP-16 package (SOT38-4); identical electrical specs and pinout; 300-mil lead spacing. | Through-hole assembly only; unsuitable for high-density SMT production or reflow processes. | Select SN74F153N only for prototyping, repair, or legacy through-hole systems requiring manual soldering. |
| 74ACT153SCX | Advanced CMOS (ACT) family; 5 V tolerant, 3.3 V compatible; 6.5 ns tPLH; 4 µA ICC (typical). | Lower power and wider voltage range, but requires careful handling of unused inputs to prevent floating nodes. | Choose 74ACT153SCX for new designs targeting mixed-voltage systems or extended battery life - verify input biasing per AC logic guidelines. |
Compared with SN74F153N and 74ACT153SCX, the N74F153D,623 offers optimal balance of proven FAST TTL speed, SO16 manufacturability, and drop-in compatibility with existing 74F-based schematics - making it preferred for volume production of commercial-grade control logic where footprint and thermal profile are constrained.
Availability
N74F153D,623 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy bus address decoding, and test equipment signal routing requiring stable component supply, long-term obsolescence management, and guaranteed traceable sourcing.
Supply support for N74F153D,623 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Philips Semiconductors (now NXP Semiconductors) is a global semiconductor leader founded in the Netherlands, specializing in analog, logic, and interface ICs for industrial, automotive, and consumer applications.
The 74F logic family - including the N74F153D,623 - was engineered for high-speed commercial-grade digital systems requiring robust noise immunity, predictable propagation delays, and seamless integration with legacy TTL infrastructure.
FAQ
What is the maximum operating frequency supported by the N74F153D,623?
The N74F153D,623 does not specify a maximum clock frequency, but its 7.0 ns typical propagation delay (In→Yn) supports reliable operation in digital systems with signal periods ≥14 ns - corresponding to a practical upper limit of approximately 70 MHz for clean edge-triggered applications. System-level timing must account for worst-case 10.5 ns max delay and interconnect skew.
Can the N74F153D,623 be used with 3.3 V logic systems?
No - the N74F153D,623 is a 5 V-only FAST TTL device requiring VCC = 4.5–5.5 V. Its input thresholds (VIL = 0.8 V, VIH = 2.0 V) and output levels (VOH ≥ 2.7 V, VOL ≤ 0.5 V) are incompatible with 3.3 V CMOS logic without level-shifting. For 3.3 V systems, consider the 74ACT153SCX instead.
Is the N74F153D,623 pin-compatible with the SN74F153N?
Yes - the N74F153D,623 (SO16, SOT109-1) and SN74F153N (DIP16, SOT38-4) share identical pin numbering, function mapping, and electrical specifications. Only the package type differs; PCB layout must be updated for SO vs. DIP footprints, but schematic symbols and net connectivity remain unchanged.
What happens to Ya and Yb when both Ea and Eb are high?
When Ea = high and Eb = high, both Ya and Yb are forced low regardless of S0, S1, or input states - per the function table's "En = H" condition. This provides a synchronous disable mode for blanking both outputs simultaneously, useful for system reset or power-down sequencing in the N74F153D,623.
Does the N74F153D,623 support hot-swap or live-insertion?
No - the N74F153D,623 lacks hot-swap protection circuitry. Applying VCC before GND, or connecting inputs before supply stabilization, may exceed absolute maximum ratings (e.g., VIK = –1.2 V clamp voltage) and cause latch-up or permanent damage. Always follow proper power sequencing: GND first, then VCC, then inputs.
N74F153D,623 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74F
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Multiplexer
- Circuit:
- 2 x 4:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 1mA, 20mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
N74F153D,623 FAQ
1.How can I place an order for N74F153D,623 through Aetrix?
Please submit a Request for Quotation (RFQ) for N74F153D,623 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for N74F153D,623 reliable?
The price and inventory of N74F153D,623 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for N74F153D,623 is usually 5 days.
3.What payment methods are accepted for N74F153D,623?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for N74F153D,623 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for N74F153D,623?
N74F153D,623 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your N74F153D,623 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for N74F153D,623?
For technical support, including N74F153D,623 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your N74F153D,623 requirements.
6.How does Aetrix verify that N74F153D,623 is sourced from the original manufacturer or authorized distributors?
All N74F153D,623 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that N74F153D,623 meets industry standards.
7.What is the process for return or replacement of N74F153D,623?
All N74F153D,623 units undergo pre-shipment inspection (PSI). If there is an issue with N74F153D,623, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The N74F153D,623 part is unused and in its original packaging.
Return procedure for N74F153D,623:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
N74F153D,623 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

