NXP Semiconductors N74F367D,623

Overview

N74F367D,623 from Nexperia is a hex non-inverting 3-state buffer/driver IC designed for bus-oriented digital systems. It features six independent channels, 5.0 ns typical propagation delay, ±64 mA low-level output sink capability, and dual active-low output enable inputs (OE0, OE1). It operates at 5 V supply within 0 °C to +70 °C and is used in address/data bus driving applications requiring high-speed isolation and load reduction.

For engineers reviewing the N74F367D,623 datasheet, N74F367D,623 pinout, N74F367D,623 application, or N74F367D,623 equivalent, key selection considerations include 3-state timing (tPZH/tPLZ ≤ 8.5 ns), input loading (20 µA HIGH/LOW), output drive strength (64 mA sink), and SO16 package compatibility with surface-mount PCB layouts.

Technical Context

The N74F367D,623 implements TTL-compatible logic with high-impedance NPN base inputs, minimizing capacitive loading on upstream drivers. Its dual enable architecture allows independent control of two groups of three buffers (Y0–Y2 and Y3–Y5), supporting segmented bus management.

All outputs are 3-state capable with defined off-state leakage (±50 µA) and short-circuit current limits (–100 to –225 mA). AC performance is specified at CL = 50 pF and RL = 500 Ω, with propagation delays guaranteed across commercial temperature range (0 °C to +70 °C).

Key Specifications

Pinout & Package

Package: SO16 - plastic small outline package, 16 leads, 3.9 mm body width, RoHS-compliant, surface-mountable.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex buffer applications.

Compared with SN74F367N and 74ACT367, the N74F367D,623 delivers optimal balance of speed (5 ns), drive strength (64 mA), and SMT compatibility in SO16 - making it preferred for high-density, high-current 5 V bus applications where legacy TTL loading remains critical.

Availability

N74F367D,623 is available at Aetrix Electronics and suitable for microprocessor address bus driving, memory data bus isolation, industrial PLC I/O expansion, and digital signal routing in test equipment requiring stable component supply and long-term sourcing continuity.

Supply support for N74F367D,623 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global leader in discrete, logic, and PowerMOS semiconductors, formed in 2017 from the former NXP Standard Products division, with focus on automotive, industrial, computing, and consumer markets.

The N74F367D,623 belongs to Nexperia's legacy 74F logic family, engineered for high-speed, high-drive 5 V TTL-compatible bus interfacing in commercial-grade embedded systems.

FAQ

What is the maximum output sink current specification for N74F367D,623?

The N74F367D,623 specifies a maximum low-level output current (IOL) of 64 mA per channel under recommended operating conditions (VCC = 5.0 V, Tamb = 25 °C). This value is guaranteed across the full commercial temperature range (0 °C to +70 °C) and enables direct drive of multiple standard TTL inputs without external amplification. The N74F367D,623 also supports short-circuit testing with IOS limits of –100 to –225 mA, though sustained shorting is prohibited per datasheet guidelines.

Does N74F367D,623 support independent enable control for its two output groups?

Yes, the N74F367D,623 provides two separate active-LOW output enable inputs: OE0 controls outputs Y0–Y2, and OE1 controls outputs Y3–Y5. This dual-enable architecture allows segmented bus control - for example, enabling upper and lower address byte lanes independently. Both enables must be LOW to activate their respective outputs; if either is HIGH, the associated outputs enter high-impedance state. This functionality is electrically verified and documented in the function table of the official Nexperia datasheet for N74F367D,623.

What is the typical propagation delay of N74F367D,623 and under what test conditions is it measured?

The typical propagation delay (tPLH/tPHL) of the N74F367D,623 is 5.0 ns, measured at VCC = 5.0 V, Tamb = 25 °C, with CL = 50 pF and RL = 500 Ω. This value reflects the time from input transition (20% to 80%) to output transition (20% to 80%) under standard AC test conditions. The datasheet guarantees a maximum delay of 7.0 ns across the full commercial temperature range (0 °C to +70 °C), ensuring timing predictability in real-world 5 V digital systems using the N74F367D,623.

Is N74F367D,623 pin-compatible with other 74F-series hex buffers like 74F365 or 74F368?

No, the N74F367D,623 is not pin-compatible with 74F365 or 74F368. The 74F365 was discontinued and replaced by the 74F367; the 74F368 is an inverting variant with different pin assignments (e.g., inverted outputs and modified enable logic). The N74F367D,623 has a unique pinout defined in its datasheet: OE0 (pin 1), I0 (pin 2), Y0 (pin 3), etc., with VCC at pin 16 and GND at pin 8. Substitution requires verification against the specific logic function, enable polarity, and pin mapping - the N74F367D,623 must be used per its published configuration.

What package type does N74F367D,623 use and what are its key mechanical characteristics?

The N74F367D,623 uses the SO16 package (SOT109-1): a plastic small outline IC with 16 leads, 3.9 mm body width, and 1.27 mm lead pitch. It conforms to JEDEC MS-012 standards, supports reflow soldering per IPC/JEDEC J-STD-020, and is RoHS-compliant. The package provides thermal resistance (RθJA) of 130 K/W and is optimized for high-density surface-mount assembly - distinguishing it from the through-hole DIP16 variant (N74F367N) which shares electrical specs but differs mechanically. This SO16 form factor is integral to the N74F367D,623's role in compact, high-speed PCB designs.