Monolithic Power Systems Inc. NB6381DL-LF-P

Overview

NB6381DL-LF-P from Monolithic Power Systems is a fully integrated, high-frequency synchronous step-down DC/DC converter delivering 8A continuous output current across a 4.5V–28V input range. It features internal 30mΩ high-side and 12mΩ low-side MOSFETs, Constant-On-Time (COT) control for fast transient response, and comprehensive protection including SCP, OCP, OVP, UVP, and thermal shutdown. It targets compact, high-efficiency point-of-load regulation in notebook I/O and optical communication systems.

For engineers reviewing the NB6381DL-LF-P datasheet, NB6381DL-LF-P pinout, NB6381DL-LF-P application, or NB6381DL-LF-P equivalent, key selection criteria include its QFN20 (3×4mm) footprint, programmable soft-start time via external capacitor, adjustable 0.8V–13V output, 200kHz–1MHz switching frequency set by resistor, and PGOOD open-drain status signaling with 1ms–2ms delay.

Technical Context

The NB6381DL-LF-P employs proprietary Constant-On-Time (COT) control with line feed-forward via the FREQ pin, enabling stable operation across wide VIN and VOUT ranges while minimizing loop compensation complexity. Its internal power stage integrates matched high- and low-side MOSFETs with precisely characterized RDS(on) values (30mΩ/12mΩ), supporting efficient CCM and skip-mode operation down to ultra-light loads.

Protection architecture includes cycle-by-cycle over-current detection with 40μs OCP hold-off and immediate SCP latch-off when FB falls below 50% of reference under short-circuit conditions. Thermal shutdown activates at 150°C with 25°C hysteresis, and UVLO ensures clean startup above 4.0V with 880mV hysteresis.

Key Specifications

Pinout & Package

Package: QFN20 (3mm × 4mm, 0.5mm pitch) with exposed thermal pad on underside for enhanced heat dissipation. Pin count and layout match JEDEC MO-220WEED package standard.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MP2451DT-LF-Z and RT7297BGQW, the NB6381DL-LF-P uniquely delivers 8A output with COT-based fast transient response, integrated 30mΩ/12mΩ MOSFETs, and full programmability (VOUT, fSW, soft-start) in a 3×4mm QFN-making it optimal for space-constrained, high-dynamic-load POL applications.

Availability

NB6381DL-LF-P is available at Aetrix Electronics and suitable for notebook I/O power, optical transceiver modules, networking PHY supplies, and FPGA core domain regulation requiring stable component supply across extended temperature and long production lifecycles.

Supply support for NB6381DL-LF-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers in the US, China, and Taiwan, and global manufacturing partnerships.

The NB6381 belongs to MPS's high-current synchronous buck converter product line, engineered specifically for compact, high-efficiency point-of-load regulation in computing, communications, and industrial systems where thermal density and transient response are critical.

FAQ

What is the minimum recommended output capacitor value for stable operation with ceramic capacitors?

A minimum 22μF X5R/X7R ceramic capacitor is required at the output when using small-ESR ceramics. This ensures sufficient capacitance to meet ripple requirements and support external ramp compensation. For 1.05V/8A operation, two 22μF 0805 capacitors in parallel are typical to reduce ESL and maintain impedance below 10mΩ at 500kHz.

How does the NB6381DL-LF-P handle light-load efficiency?

The NB6381DL-LF-P automatically enters skip mode below the critical current threshold (~1.2A at 12V→1.05V), where the high-side MOSFET turns on less frequently to reduce switching losses. In this mode, the low-side MOSFET driver enters high-Z state at zero inductor current, and a current modulator limits residual discharge to <600μA-maintaining >85% efficiency at 10mA load.

Can the NB6381DL-LF-P be synchronized to an external clock?

No-the NB6381DL-LF-P uses Constant-On-Time (COT) control with resistor-programmed frequency and has no external clock sync input. Frequency is set solely by the resistor on the FREQ pin and varies slightly with input voltage due to feed-forward architecture. For synchronization, a current-mode controller like the MP2451 or RT7297 would be required.

What is the maximum allowable PCB trace length between IN and PGND pins?

IN and PGND traces must be kept under 3mm in length and use ≥15mil width with ≥2 vias per pin to the thermal pad. Longer traces increase input loop inductance, degrading EMI performance and causing voltage spikes at SW node during turn-off-potentially triggering false OCP or damaging the internal MOSFETs.

Does the PGOOD pin require an external pull-up resistor, and what value is recommended?

Yes-PGOOD is an open-drain output and requires an external pull-up. A 100kΩ resistor to VCC is recommended for standard operation; values between 47kΩ and 470kΩ are acceptable. Lower values improve noise immunity but increase quiescent current; higher values risk slow rise time in high-capacitance bus environments.

Is the exposed thermal pad electrically connected to any internal node?

Yes-the exposed pad is internally connected to PGND and must be soldered to a solid PGND copper pour with ≥6 thermal vias (0.3mm diameter) to an inner ground plane. Failure to connect the pad results in excessive junction temperature (>150°C at 5A), triggering thermal shutdown and potential reliability degradation.

What happens during undervoltage lockout (UVLO) release?

When VIN rises above 4.0V (typical), the NB6381DL-LF-P exits UVLO and initiates soft-start after a 100μs internal delay. The EN pin remains inactive until UVLO is cleared; if EN is held high during UVLO, the device waits for VIN to stabilize before beginning SS ramp-preventing premature startup during rail ramp-up.