Monolithic Power Systems Inc. NB650HGL-Z

Overview

NB650HGL-Z from Monolithic Power Systems is a fully-integrated, synchronous step-down DC/DC converter delivering 6A continuous output current with dynamic 2-bit VID voltage scaling. It operates from 4.5V to 28V input, regulates output from 0.6V to 13V, and uses Constant-On-Time (COT) control for fast transient response in notebook I/O and distributed power systems.

For engineers reviewing the NB650HGL-Z datasheet, NB650HGL-Z pinout, NB650HGL-Z application, or NB650HGL-Z equivalent, this device requires attention to BST capacitor layout, VID resistor network selection, thermal pad soldering, and soft-start capacitor sizing to ensure stable 6A operation under fast load steps.

Technical Context

The NB650HGL-Z implements a proprietary COT control architecture with internal 50mΩ high-side and 18mΩ low-side MOSFETs, enabling cycle-by-cycle current limiting and sub-200ns minimum on-time. Its feedback loop references a 600mV ±6mV precision bandgap, with programmable frequency (150kHz–1MHz) via external resistor on FREQ pin.

VID inputs (VID1/VID2) directly control internal parallel FB-divider switches (RFB1/RFB2), enabling four discrete output voltages without external controller intervention. Protection logic includes hiccup-mode OCP/SCP, non-latching UVP/OVP (0.4V/0.8V FB thresholds), and thermal shutdown at 150°C with 25°C hysteresis.

Key Specifications

Pinout & Package

Package: QFN17 (3mm × 4mm) with exposed thermal pad on underside - requires solder paste stencil design and ≥6 thermal vias for 2.4W dissipation at +25°C ambient.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with MPQ4572GQB-A and RTQ2134BGQW, the NB650HGL-Z delivers superior transient response via COT architecture and integrates VID-controlled FB scaling without external logic-making it optimal for compact, multi-rail consumer electronics where layout area and dynamic voltage agility are critical.

Availability

NB650HGL-Z is available at Aetrix Electronics and suitable for notebook I/O power, networking system rails, and flat-panel display logic requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for NB650HGL-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of expertise in DC/DC conversion and motor control.

The NB650/NB650H product line targets space-constrained, high-transient consumer and computing applications-designed to replace multi-chip solutions with fully integrated, thermally optimized buck converters featuring dynamic voltage control.

FAQ

What is the purpose of the BST pin and how must it be implemented?

The BST pin supplies the floating gate drive voltage for the internal high-side MOSFET. It requires a 0.1µF X7R ceramic capacitor connected between BST and SW pins, placed within 2mm of the IC. This capacitor must withstand ≥6V rating and be routed with minimal loop area to prevent bootstrap charge loss and ensure reliable HS-FET turn-on across all operating conditions.

How does the 2-bit VID interface change the output voltage without external components?

The VID1/VID2 inputs control internal NMOS switches (RFB1/RFB2) that parallel with external FB divider resistors (R2A/R2B/R2C). Each VID code alters the effective R2 value, shifting the FB node voltage relationship and thus the regulated output. No DAC, microcontroller, or additional passives are needed-voltage changes occur synchronously with VID state transitions.

Why does the NB650HGL-Z use Constant-On-Time control instead of voltage-mode PWM?

COT control eliminates the need for external loop compensation by making switching frequency inversely proportional to input/output voltage ratio. This yields inherently stable operation with ceramic output capacitors, achieves <10µs load-step response, and simplifies design across varying input rails-critical for battery-powered and dynamically scaled systems where traditional error-amplifier-based loops would require complex tuning.

What distinguishes hiccup-mode OCP in NB650H from latch-off in NB650?

In hiccup mode (NB650H), the device disables switching, discharges the SS capacitor, waits for thermal recovery, then attempts restart-repeating until fault clears. In contrast, NB650 latches off permanently and requires full power cycle. Hiccup mode enables autonomous recovery in remote or inaccessible deployments like network edge devices without manual intervention.

Can the NB650HGL-Z operate reliably with only ceramic output capacitors?

Yes, but an external ramp circuit (R4/C4) is required for stability in PWM mode due to low ESR. The ramp compensates for insufficient VFB ripple slope; equations in the datasheet define R4/C4 values based on VIN, VOUT, and inductor parameters. Without it, subharmonic oscillation or jitter may occur-especially at light loads or high frequencies.

What is the minimum recommended soft-start capacitor value and why?

The minimum soft-start capacitor is 4.7nF when output capacitance exceeds 330µF. This ensures controlled inrush current during startup, preventing input rail collapse and avoiding false triggering of UVLO or OCP. Smaller values risk excessive dI/dt through input capacitors and can cause system-level brownouts in shared power domains.

How does the PG pin behave during startup and fault conditions?

The PG pin remains low (pulled to GND) until FB reaches 90% of 600mV (540mV), then asserts high after a fixed 0.5ms delay. During OVP/UVP or thermal shutdown, PG goes low immediately upon fault detection. Its open-drain structure allows flexible pull-up to any compatible rail (e.g., 3.3V or 5V), enabling direct interfacing with FPGA or PMIC sequencers.