Monolithic Power Systems Inc. NB672GL-Z
- Part No.:
- NB672GL-Z
- Manufacturer:
- Monolithic Power Systems Inc.
- Package:
- 21-PowerVFQFN
- Datasheet:
-
NB672GL-Z.pdf
- Description:
- IC REG BUCK ADJ 6A 21QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NB672GL-Z from Monolithic Power Systems is a 24V-input, high-current synchronous buck converter with integrated ±1.5A VTT LDO and buffered VTTREF reference, designed for DDR3/DDR3L/LPDDR2 memory power delivery. It delivers 6A continuous / 8A peak output current (VDDQ), supports 0.604V–5.5V adjustable output, and employs Constant-On-Time (COT) control for fast transient response in laptop and server memory subsystems.
For engineers reviewing the NB672GL-Z datasheet, NB672GL-Z pinout, NB672GL-Z application, or NB672GL-Z equivalent, key selection criteria include its QFN21 (3mm×4mm) package, dual enable control (EN1/EN2) for S0/S3/S4 states, integrated VTT/VTTREF tracking accuracy (±20 mV), and COT-based stability with ceramic-only output capacitors.
Technical Context
The NB672GL-Z integrates three tightly coupled power rails: a primary synchronous buck regulator (VDDQ) using internal 28 mΩ/10 mΩ MOSFETs and COT control; a ±1.5A sink/source VTT LDO referenced to VTTREF; and a buffered VTTREF output that tracks VDDQ/2 with ±1% accuracy. Its dual enable logic (EN1/EN2) enables precise power-state sequencing across S0 (full on), S3 (VDDQ+VTTREF active, VTT high-Z), and S4/S5 (all off).
Protection architecture includes valley-current OCP (8.5A typ), 125% VREF overvoltage lockout with 2.5 μs delay, 55% VREF undervoltage lockout with 12 μs delay, thermal shutdown at 150°C, and open-drain power-good (PG) signaling with 450 μs delay and 95%/85% VREF thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5V to 22V - Supports wide industrial and computing input rails including 12V and 19V adapter supplies. |
| VDDQ Output Current | 6A continuous / 8A peak - Sustains DDR3 memory burst loads without external current sharing. |
| Switching Frequency | 500 kHz typical - Enables compact magnetics and predictable EMI profile in dense PCB layouts. |
| VTT LDO Capability | ±1.5A sink/source - Fully powers DDR termination without external FETs or discrete regulators. |
| VTTREF Tracking Accuracy | ±1% of VDDQ/2 - Ensures precise VTT regulation critical for DDR3 signal integrity and margin. |
| Thermal Shutdown | 150°C with 25°C hysteresis - Prevents permanent damage during sustained overload or poor heatsinking. |
| Enable Control Logic | EN1/EN2 dual digital inputs - Enables hardware-controlled S0/S3/S4 power state transitions per JEDEC spec. |
Pinout & Package
Package: QFN21 (3mm × 4mm, 0.5mm pitch) with exposed thermal pad on underside for enhanced heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 BST | Bootstrap supply | Provides floating gate drive voltage for high-side MOSFET; requires 0.1μF ceramic capacitor between BST and SW. |
| 2,3 SW | Power switch node | Connects to inductor and bootstrap capacitor; carries full switching current and must use short/wide copper traces. |
| 4 VTTREF | Buffered reference output | Tracks VDDQ/2 with ±1% accuracy; requires ≥0.22μF X7R/X5R ceramic decoupling close to pin. |
| 5 VDDQSEN | VDDQ output sense | Direct Kelvin connection to VDDQ output capacitor for accurate feedback and load regulation. |
| 6 VINLDO | VTT LDO input | Typically tied to VDDQ rail; supplies input to ±1.5A VTT LDO stage. |
| 7 VTT | VTT LDO output | Delivers ±1.5A termination current; requires ≥10μF X7R/X5R ceramic decoupling at pin. |
| 8 AGND | Analog ground reference | Reference point for internal 0.604V feedback reference; FB divider must connect here for best regulation. |
| 9 VTTSEN | VTT output sense | Direct Kelvin connection to VTT output capacitor; separates high-current path from sensing trace. |
| 10,11,20,21 PGND | Power ground | Low-impedance return for high-current paths; requires multiple vias to internal ground plane. |
| 12,19 VIN | Main input supply | Accepts 5V–22V input; requires bulk and high-frequency input capacitance near pin. |
| 13 PG | Power good indicator | Open-drain output pulled low until VDDQ reaches 95% VREF; 450 μs delay ensures stable regulation. |
| 14 FB | Feedback input | Sets VDDQ via resistor divider; 10nA bias current enables high-impedance dividers minimizing quiescent loss. |
| 15 EN1 / 17 EN2 | Digital enable inputs | Control power states: S0 (both high), S3 (EN1=low, EN2=high), S4/S5 (both low). |
| 16 VCC | Internal 5.1V LDO output | Powers internal logic and gate drivers; requires ≥1μF ceramic decoupling for noise immunity. |
| 18 NC | No connect | Not internally bonded; must remain unconnected and unrouted. |
Key Features
| Feature | Design Value |
|---|---|
| Constant-On-Time (COT) control | Enables fast load transient response (<10 μs recovery) and stable operation with ceramic-only output capacitors. |
| Integrated VTT/VTTREF subsystem | Eliminates need for external op-amps, references, or discrete LDOs in DDR3 memory power trees. |
| Dual enable (EN1/EN2) sequencing | Hardware-enables JEDEC-compliant S0/S3/S4 power state transitions without microcontroller intervention. |
| Valley-current overcurrent protection | Detects low-side MOSFET RDS(ON) voltage during conduction to trigger cycle-by-cycle current limiting at 8.5A typ. |
| Internal soft-start | 1.95 ms ramp time prevents inrush current and output overshoot during power-up. |
Applications
| Laptop DDR3 Memory Power | Server Memory Subsystem |
|---|---|
Use Scenario: Providing VDDQ, VTT, and VTTREF to DDR3 SO-DIMMs in thin-and-light notebooks with 12V or 19V input adapters. IC Role / Device Role / Timing Role: Primary memory power controller delivering regulated 1.5V VDDQ, ±1.5A VTT, and precision VTTREF with JEDEC S3 state support. Use Value: Reduces BOM count by 7+ components versus discrete solutions while maintaining <±20mV VTT regulation under dynamic load. | Use Scenario: Powering multi-rank DDR3 RDIMMs in 1U/2U rack servers where thermal density and layout area are constrained. IC Role / Device Role / Timing Role: High-density memory PMIC managing VDDQ regulation, VTT termination, and VTTREF tracking across dual-channel DIMM slots. Use Value: Enables 6A VDDQ per channel with 500kHz switching, reducing inductor size by 40% vs. 300kHz alternatives while meeting DDR3 timing margins. |
| Flat Panel Display Memory | Networking System DDR3 Interface |
Use Scenario: Supplying DDR3 memory for video frame buffers and graphics processing in 4K UHD LCD/LED displays. IC Role / Device Role / Timing Role: Single-chip DDR3 power solution supporting VDDQ adjustment (1.2V–1.5V) and VTTREF tracking for varying display resolutions. Use Value: Maintains ±1% VTTREF tracking across temperature (−40°C to +125°C), ensuring signal integrity for high-speed video data paths. | Use Scenario: Powering DDR3 memory in network processors, switches, and baseband units requiring low-noise, sequenced power-up. IC Role / Device Role / Timing Role: Memory PMIC with EN1/EN2-controlled S0→S3 transition to suspend VTT during low-power packet processing modes. Use Value: Achieves >85% efficiency at 1A load and <100μA shutdown current, extending system standby time without compromising VDDQ stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DDR3 memory power delivery applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2494D | Single-output 6A buck only; no integrated VTT/VTTREF; requires external LDO and reference. | Used where DDR3 termination is handled separately or not required (e.g., LPDDR2-only designs). | Select when only VDDQ regulation is needed and board space allows discrete VTT implementation. |
| RTQ2134C-QA | 3-output PMIC (VDDQ/VTT/VTTREF); 4A VDDQ; supports DDR4; automotive AEC-Q100 qualified. | Targeted at automotive infotainment with DDR4 memory; higher cost and qualification overhead. | Select only for AEC-Q100-compliant systems requiring DDR4 support; not drop-in for NB672GL-Z. |
Compared with MP2494D and RTQ2134C-QA, the NB672GL-Z uniquely integrates all three DDR3 rails (VDDQ/VTT/VTTREF) in one QFN21 package with JEDEC S3 sequencing-offering lowest component count and smallest footprint for DDR3-specific computing applications.
Availability
NB672GL-Z is available at Aetrix Electronics and suitable for laptop computers, server memory modules, and flat-panel display controllers requiring stable component supply and long-term obsolescence management.
Supply support for NB672GL-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with over two decades of leadership in DC/DC conversion and power management.
The NB672GL-Z belongs to MPS's DDR memory power management product line, engineered specifically to consolidate VDDQ, VTT, and VTTREF into a single-package solution for space-constrained, high-efficiency DDR3/DDR3L systems.
FAQ
What is the maximum input voltage rating for NB672GL-Z?
The absolute maximum input voltage (VIN) is 24V, but the recommended operating range is 5V to 22V. Operation above 22V risks exceeding internal MOSFET breakdown limits and reduces reliability; sustained use at 24V is not advised per datasheet Section "Recommended Operating Conditions".
Can NB672GL-Z be used for DDR4 memory applications?
No. The NB672GL-Z is specified for DDR3, DDR3L, and LPDDR2 memory only. DDR4 requires tighter VTTREF tracking (±0.5%), lower VDDQ tolerance (±25mV), and different S3/S4 sequencing-capabilities not supported by this device's architecture or electrical specifications.
How does the EN1/EN2 pin combination affect VTT behavior in S3 mode?
In S3 mode (EN1 = low, EN2 = high), the VTT LDO is disabled and placed in high-impedance state-neither sourcing nor sinking current. VDDQ and VTTREF remain active, allowing memory to retain data while terminating current is removed to reduce standby power, per JEDEC JESD79-3 specification.
What is the minimum output capacitance required for stable VTT regulation?
A minimum 10μF X7R or X5R ceramic capacitor is required directly at the VTT pin. This value ensures sufficient charge reservoir for ±1.5A transient currents and maintains loop stability; smaller values risk VTT droop during fast sink/source transitions and violate design guidelines in Section "VTT LDO".
Is NB672GL-Z pin-compatible with NB673GL-Z?
Yes-both share identical QFN21 (3mm×4mm) package, pinout, and footprint. However, NB673GL-Z delivers 8A/10A (continuous/peak) VDDQ current versus NB672GL-Z's 6A/8A, due to lower RDS(ON) MOSFETs (24 mΩ/9 mΩ vs. 28 mΩ/10 mΩ); substituting requires verifying thermal margin and inductor saturation current.
Does NB672GL-Z support external ramp compensation?
Yes-the device includes internal ramp compensation for ceramic-capacitor stability, but external ramp (R4/C4 network) can be added if instability occurs under specific conditions (e.g., very low ESR output caps or extreme duty cycles). Design equations and layout guidance are provided in Section "Operating with external ramp compensation".
NB672GL-Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Monolithic Power Systems Inc.
- Series:
- -
- Package/Case:
- 21-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 5V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 0.604V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 6A
- Frequency - Switching:
- 500kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 21-QFN (3x4)
NB672GL-Z FAQ
1.How can I place an order for NB672GL-Z through Aetrix?
Please submit a Request for Quotation (RFQ) for NB672GL-Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NB672GL-Z reliable?
The price and inventory of NB672GL-Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NB672GL-Z is usually 5 days.
3.What payment methods are accepted for NB672GL-Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NB672GL-Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NB672GL-Z?
NB672GL-Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NB672GL-Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NB672GL-Z?
For technical support, including NB672GL-Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NB672GL-Z requirements.
6.How does Aetrix verify that NB672GL-Z is sourced from the original manufacturer or authorized distributors?
All NB672GL-Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NB672GL-Z meets industry standards.
7.What is the process for return or replacement of NB672GL-Z?
All NB672GL-Z units undergo pre-shipment inspection (PSI). If there is an issue with NB672GL-Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NB672GL-Z part is unused and in its original packaging.
Return procedure for NB672GL-Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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