Monolithic Power Systems Inc. NB673GL-Z

Overview

NB673GL-Z from Monolithic Power Systems is a 24V, high-current synchronous buck converter with integrated ±1.5A VTT LDO and buffered VTTREF reference, designed for DDR3/DDR3L/LPDDR2 memory power delivery. It delivers 8A continuous / 10A peak output current, employs Constant-On-Time (COT) control for fast transient response, and operates across 5–22V input with adjustable VDDQ (0.604–5.5V). Used in laptop and server memory subsystems requiring compact, high-density power solutions.

For engineers reviewing the NB673GL-Z datasheet, NB673GL-Z pinout, NB673GL-Z application, or NB673GL-Z equivalent, key selection criteria include its dual-regulator architecture (VDDQ buck + VTT LDO), COT control stability with ceramic output capacitors, ±45mV VTT tracking accuracy, 500kHz switching frequency, and multi-state enable logic (S0/S3/S4-S5) for DDR memory power sequencing.

Technical Context

The NB673GL-Z integrates three tightly coupled power rails: a primary synchronous buck regulator (VDDQ) using internal 24mΩ/9mΩ MOSFETs and COT control; a ±1.5A sink/source VTT LDO referenced to VTTREF; and a buffered, 1% accurate VTTREF that tracks VDDQ/2. Its valley-current OCP uses low-side R_DS(ON) sensing without external sense resistors.

Enable logic supports three operational states via EN1/EN2: S0 (all regulators active), S3 (VDDQ + VTTREF on, VTT in high-Z), and S4/S5 (all off with discharge). Power Good (PG) provides open-drain status with 450μs delay and 95%/85% VREF thresholds, while internal soft-start ensures monotonic VDDQ ramp-up.

Key Specifications

Pinout & Package

Package: QFN21 (3mm × 4mm) with exposed thermal pad on underside for enhanced heat dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current DDR memory power delivery applications.

Compared with NB673GL-Z, MP2494D-LF-Z reduces integration but increases BOM complexity for DDR systems, while RTQ2134GSP-QA offers partial integration but lacks the ±1% VTTREF tracking essential for DDR3L compliance-making NB673GL-Z uniquely suited for fully self-contained memory power designs.

Availability

NB673GL-Z is available at Aetrix Electronics and suitable for laptop computers, server memory subsystems, and flat-panel display controllers requiring stable component supply and long-term lifecycle support.

Supply support for NB673GL-Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with core expertise in DC/DC conversion, motor drivers, and battery management.

The NB673GL-Z belongs to MPS's DDR memory power management product line, engineered specifically to consolidate VDDQ, VTT, and VTTREF functions into a single high-density package for next-generation computing platforms.

FAQ

What is the recommended input capacitor configuration for NB673GL-Z?

A minimum 22μF low-ESR ceramic capacitor placed within 3mm of VIN and PGND pins is required, supplemented by a 100μF bulk electrolytic or polymer capacitor on the main input rail. This dual-stage approach suppresses both high-frequency switching noise and low-frequency line ripple, ensuring stable operation across 5–22V input range and preventing UVLO triggering during transients.

How does the NB673GL-Z handle pre-biased output conditions during startup?

When the FB node is pre-biased above the soft-start target voltage, the NB673GL-Z disables both high-side and low-side MOSFETs until the internal reference voltage exceeds the sensed FB voltage. This prevents reverse current flow into the output capacitor and ensures monotonic VDDQ ramp-up without output voltage overshoot or instability.

Can NB673GL-Z operate with 100% duty cycle at low input voltages?

No. The NB673GL-Z uses a constant-on-time architecture with minimum off-time of 250–350ns, preventing true 100% duty cycle operation. At VIN ≤ VDDQ + (I_LOAD × R_{DS(ON)_HS}), the device enters dropout mode where regulation degrades, and VDDQ follows VIN minus conduction losses-requiring careful input voltage margining in low-VIN applications.

What is the purpose of the AGND pin, and how should it be routed?

AGND serves as the dedicated analog reference ground for the internal 0.604V feedback reference and FB comparator. It must be connected to a clean, low-noise ground plane separate from PGND traces, with the FB resistor divider grounded directly to AGND-not PGND-to avoid load regulation errors caused by PGND IR drop under high current.

Is NB673GL-Z compatible with DDR4 memory systems?

No. The NB673GL-Z is specified for DDR3, DDR3L, and LPDDR2 memory standards only. DDR4 requires different VDDQ (1.2V nominal) and VTT (0.6V) voltage levels, tighter VTTREF tracking (±0.5%), and higher current slew rates-features not supported by this device's fixed reference architecture and output stage design.

How does the valley-current OCP detect overloads without an external sense resistor?

The NB673GL-Z monitors the voltage drop across the internal low-side MOSFET's R_DS(ON) (9mΩ typical) during its ON state. When this voltage exceeds the internal threshold corresponding to 8.5–10.5A, the controller terminates the current cycle. This eliminates external sensing components while maintaining accuracy within ±10% across temperature and process variation.

What is the function of the NC pin (Pin 18), and can it be tied to ground?

Pin 18 is a no-connect (NC) terminal with no internal bond wire or circuit connection. It must remain electrically floating-neither grounded nor connected to any net. Routing copper to or near this pin may cause parasitic coupling or mechanical stress on the die; best practice is to leave it unmasked or covered with solder mask.