Monolithic Power Systems Inc. NB677GQ-P

Overview

NB677GQ-P from Monolithic Power Systems is a fully integrated 5.5V–24V input, 3.3V fixed-output synchronous buck converter with integrated 100mA LDO and 300kHz CLK output, delivering 8A continuous / 10A peak output current in a QFN-16 (3mm×3mm) package. It employs Constant-On-Time (COT) control, features internal 26mΩ/12mΩ MOSFETs, and supports laptop power rails requiring fast transient response and compact DC/DC conversion.

For engineers reviewing the NB677GQ-P datasheet, NB677GQ-P pinout, NB677GQ-P application, or NB677GQ-P equivalent, key selection criteria include its dual-regulator architecture (buck + LDO), PG signal timing (0.5ms delay), COT loop stability with ceramic output caps, and EN/ENLDO logic state table for sequencing control in portable systems.

Technical Context

The NB677GQ-P integrates a high-efficiency synchronous buck stage with proprietary switching loss reduction and an independent 3.3V/100mA LDO that switches over to VOUT once regulation is established. Its COT control uses VFB sensing against a 3.35V reference with 95%–105% PG thresholds and 0.5ms PG assertion delay.

Protection includes valley-current OCP (9A typ), 130% OVP latch-off, 60% UVP latch-off, thermal shutdown at 150°C with 25°C hysteresis, and UVLO at 4.65V on VCC. The 300kHz CLK output drives external charge pumps without loading the main regulator.

Key Specifications

Pinout & Package

Package: QFN-16 (3mm × 3mm), exposed thermal pad, RoHS-compliant, lead-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-current synchronous buck converter applications.

Compared with MP2451DT-LF-Z and RT7297CGJ6F, the NB677GQ-P uniquely integrates 8A buck, 100mA LDO, and 300kHz CLK in one QFN-16 package-enabling single-chip 3.3V system power with guaranteed PG timing and autonomous LDO switchover, critical for laptop and tablet designs.

Availability

NB677GQ-P is available at Aetrix Electronics and suitable for laptop computer power delivery, tablet PC core rails, and flat panel display logic supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for NB677GQ-P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Monolithic Power Systems (MPS) is a fabless semiconductor company specializing in high-performance analog and power ICs, with design centers across Asia and North America.

The NB677GQ-P belongs to MPS's high-current integrated DC/DC converter product line, engineered for space-constrained portable computing and display systems requiring combined buck, LDO, and clock generation in a single chip.

FAQ

What is the recommended input capacitor configuration for NB677GQ-P?

Use ≥22µF X7R/X5R ceramic capacitor placed directly at the VIN pin with short, wide traces and multiple vias to PGND. A second 100nF ceramic should be placed adjacent to the VCC pin. Total input capacitance must handle peak ripple current; parallel 10µF + 2.2µF ceramics are typical for 24V input systems.

How does the LDO switch-over function work, and when does it activate?

The internal 3.3V LDO activates at power-up and supplies auxiliary loads until VOUT reaches ≥3.15V and PG asserts (after 0.5ms delay). At that point, an internal MOSFET connects LDO output to VOUT, disabling the LDO regulator to improve efficiency. This switch-over is automatic and requires no external control.

Can NB677GQ-P operate with 100% ceramic output capacitors?

Yes. Unlike traditional COT controllers, NB677GQ-P includes internal ramp compensation that ensures stability with zero-ESR ceramic output capacitors-eliminating need for tantalum or aluminum electrolytics and reducing output ripple by >40%.

What is the purpose of the CLK output, and what load can it drive?

The 300kHz CLK output drives external charge pump circuits (e.g., Dickson topology) to generate ~12–15V gate drive voltages for external load switches. It sources/sinks ±5mA and maintains rail-to-rail swing (3.1–3.4V) into 100pF load; no series resistor needed for standard pump ICs.

How is over-current protection implemented, and what happens during a fault?

OCP uses valley-current sensing on the low-side MOSFET's R_DS(ON), tripping at 9A typical. Upon fault, the controller halts switching, pulls PG low, and latches off-requiring EN low or VIN power cycle to reset. No auto-retry occurs to prevent thermal runaway.

Is NB677GQ-P suitable for new designs despite the "NOT RECOMMENDED FOR NEW DESIGNS" notice?

No. The datasheet explicitly states "NOT RECOMMENDED FOR NEW DESIGNS" due to MPS's end-of-life roadmap. While functional and supported for existing production, Aetrix recommends evaluating MPQ4470-A or MPQ4420A as drop-in replacements with extended lifetime, enhanced efficiency, and active technical support.

What layout guidance applies to the AGND and PGND connections?

AGND must be routed as a dedicated analog ground plane under the IC, isolated from noisy power planes, and connected to PGND at a single point near the thermal pad. PGND traces (especially SW, VIN, PGND pins) require wide copper, multiple thermal vias to inner ground layers, and minimal loop area to suppress EMI and ensure accurate current sensing.