onsemi NC7WV07L6X_F065
- Part No.:
- NC7WV07L6X_F065
- Manufacturer:
- onsemi
- Package:
- 6-UFDFN
- Datasheet:
-
NC7WV07L6X_F065.pdf
- Description:
- IC BUF NON-INVERT 3.6V 6MICROPAK
- Quantity:
- Payment:

- Shipping:

Inventory:1,269
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Product details
Overview
NC7WV07L6X_F065 from onsemi is a dual open-drain buffer IC designed for ultra-low-power logic interfacing in space-constrained applications. It operates from 0.9 V to 3.6 V, delivers 1.6 ns propagation delay at 3.3 V (typ), supports 24 mA output drive, and features IOFF partial power-down protection. It is used in level-shifting I²C buses and mixed-voltage GPIO expansion.
For engineers reviewing the NC7WV07L6X_F065 datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain compatibility with 3.6 V-tolerant inputs, sub-2 ns timing at 3.3 V, MicroPak™ package footprint (1.45 mm × 1.0 mm), and IOFF-enabled system-level power sequencing.
Technical Context
The NC7WV07L6X_F065 implements two independent non-inverting buffers with open-drain outputs, enabling wired-AND logic and bidirectional bus operation. Its IOFF circuitry disables input/output leakage when VCC = 0 V, supporting hot-insertion and partial power-down modes.
All inputs tolerate up to 3.6 V regardless of VCC (0.9–3.6 V), allowing seamless interfacing between 1.2 V, 1.8 V, 2.5 V, and 3.3 V domains. Propagation delay varies from 15.9 ns at 0.9 V to 1.6 ns at 3.3 V (typ), with guaranteed performance across −40°C to +85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.9 V to 3.6 V - enables single-supply operation across multiple low-voltage logic families. |
| tPD (Typ) | 1.6 ns at VCC = 3.3 V - ensures fast signal routing in high-speed digital control paths. |
| IOFF Leakage | ≤0.5 µA at VCC = 0 V - prevents back-powering and maintains isolation during power sequencing. |
| Output Drive | 24 mA sink at VCC = 3.3 V - supports standard I²C pull-up loads and fan-out to multiple CMOS inputs. |
| Input Tolerance | Up to 3.6 V independent of VCC - eliminates external level shifters in mixed-voltage interconnects. |
| Package | MicroPak™ (SIP6, 1.45 mm × 1.0 mm) - provides minimal PCB area for ultra-dense portable electronics. |
Pinout & Package
NC7WV07L6X_F065 is housed in the MicroPak™ package (Case 127EB), a 6-terminal leadless package with bottom-side solder pads and no exposed leads. Pin 1 is marked by a microdot in Q4 orientation per tape-and-reel specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input 1 | Non-inverting logic input for first buffer channel; 3.6 V tolerant regardless of VCC. |
| 2 (GND) | Ground | Reference return path for both channels; must be connected to system ground plane. |
| 3 (A2) | Input 2 | Non-inverting logic input for second buffer channel; electrically isolated from A1. |
| 4 (Y2) | Output 2 (open-drain) | Open-drain output requiring external pull-up; sinks current only, no active high drive. |
| 5 (VCC) | Supply | Single positive supply input (0.9–3.6 V); powers internal logic and IOFF circuitry. |
| 6 (Y1) | Output 1 (open-drain) | Independent open-drain output; supports wired-AND with Y2 or other open-drain devices. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power operation | ICC ≤ 0.9 µA max at VCC = 0.9–3.6 V - reduces quiescent current in battery-powered IoT nodes. |
| IOFF partial power-down | Input/output leakage ≤ 0.5 µA when VCC = 0 V - enables safe hot-swap and multi-rail sequencing. |
| Wide voltage input tolerance | Inputs functional up to 3.6 V even at VCC = 0.9 V - eliminates need for discrete level translators. |
| Low capacitive loading | CIN = 2.0 pF, COUT = 6.5 pF - minimizes signal distortion and timing skew in high-frequency GPIO paths. |
Applications
| I²C Bus Level Shifting | GPIO Expansion Interface |
|---|---|
Use Scenario: Interfacing a 3.3 V microcontroller I²C master with 1.8 V sensors on the same bus. IC Role / Device Role / Timing Role: Dual open-drain buffer providing bidirectional voltage translation without direction control pins. Use Value: Eliminates dedicated level-shifter ICs while maintaining I²C timing compliance via 1.6 ns tPD and 3.6 V-tolerant inputs. |
Use Scenario: Extending GPIO count of an ultra-low-power MCU using a shared 1.2 V supply rail. IC Role / Device Role / Timing Role: Dual buffer isolating MCU pins from peripheral loads while enabling flexible pull-up configuration. Use Value: Supports 0.9 V operation and IOFF to prevent backfeed during MCU sleep, reducing system standby current. |
| Mixed-Voltage Sensor Hub | Hot-Swappable Module Interface |
Use Scenario: Aggregating analog sensor outputs (1.8 V ADC interface) and digital status lines (3.3 V FPGA) into one hub ASIC. IC Role / Device Role / Timing Role: Voltage-domain decoupling element ensuring signal integrity across supply boundaries. Use Value: Input overvoltage tolerance and open-drain outputs allow direct connection to diverse logic families without clamping diodes. |
Use Scenario: Enabling hot-plug insertion of daughterboards powered by independent supplies into a main controller chassis. IC Role / Device Role / Timing Role: Isolation gate preventing power domain interaction during insertion/removal sequences. Use Value: IOFF functionality guarantees <0.5 µA leakage when VCC is unpowered, meeting IEC 61000-4-2 system-level ESD robustness requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual open-drain buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NC7WZ07L6X | Higher speed (1.2 ns tPD at 3.3 V), but rated only for VCC = 1.65–5.5 V - no 0.9 V support. | Not suitable for sub-1.2 V systems; lacks IOFF and 3.6 V input tolerance below 1.65 V VCC. | Select when operating exclusively ≥1.65 V and timing margin is critical; avoid for battery-critical 0.9 V designs. |
| SN74LVC2G07DCKR | Same MicroPak (SC70-6) package, 1.65–5.5 V VCC range, 32 mA drive, but no IOFF or <1.2 V operation. | Requires external power sequencing controls; incompatible with deep-sleep partial-power-down architectures. | Prefer for industrial 3.3 V systems needing higher drive strength; not drop-in for ultra-low-voltage or hot-swap use cases. |
Compared with NC7WV07L6X_F065, NC7WZ07L6X offers faster timing but sacrifices sub-1.2 V operation and IOFF, while SN74LVC2G07DCKR provides greater drive but lacks true low-voltage compatibility and power-down isolation - making NC7WV07L6X_F065 uniquely suited for energy-constrained, multi-rail embedded systems.
Availability
NC7WV07L6X_F065 is available at Aetrix Electronics and suitable for I²C level shifting, GPIO expansion, mixed-voltage sensor hubs, and hot-swappable module interfaces requiring stable component supply and long-term design continuity.
Supply support for NC7WV07L6X_F065 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Semiconductor Components Industries, LLC) is a global semiconductor supplier focused on energy-efficient technologies for automotive, industrial, cloud, and IoT applications.
The TinyLogic® ULP-A family - including NC7WV07L6X_F065 - was engineered for ultra-low-power, small-footprint logic interfacing in battery-powered and space-constrained electronics.
FAQ
What is the minimum operating voltage for NC7WV07L6X_F065?
The NC7WV07L6X_F065 supports a minimum VCC of 0.9 V, verified across the full temperature range (−40°C to +85°C). This enables direct integration with sub-1.2 V microcontrollers and energy-harvesting subsystems where supply headroom is constrained. Operation below 0.9 V is not characterized or guaranteed.
Does NC7WV07L6X_F065 support hot-swap or partial power-down?
Yes, NC7WV07L6X_F065 includes IOFF circuitry that actively disables input and output leakage paths when VCC = 0 V, limiting current to ≤0.5 µA. This allows safe insertion/removal of modules powered independently and prevents back-powering of unpowered rails - a key requirement in modular industrial and telecom systems.
Can NC7WV07L6X_F065 interface a 3.3 V input with a 1.2 V supply rail?
Yes. NC7WV07L6X_F065 inputs tolerate up to 3.6 V regardless of VCC, so a 3.3 V signal applied to A1 or A2 remains valid even when VCC = 1.2 V. The output Y1/Y2 will reflect the input state (low or high-impedance) without damage or latch-up, enabling robust level translation without external components.
What is the maximum output sink current for NC7WV07L6X_F065 at 3.3 V?
At VCC = 3.3 V and TA = 25°C, NC7WV07L6X_F065 guarantees 24 mA sink capability per output (Y1 or Y2) with VOL ≤ 0.55 V. This meets I²C standard-mode pull-down requirements and supports driving multiple CMOS loads or LED indicators directly through external pull-ups.
Is NC7WV07L6X_F065 RoHS compliant and lead-free?
Yes, NC7WV07L6X_F065 is Pb-free, halogen-free/BFR-free, and fully RoHS compliant per EU Directive 2011/65/EU. The MicroPak™ package uses matte tin surface finish and conforms to JEDEC J-STD-020 moisture sensitivity level 1, supporting standard reflow profiles without preconditioning.
NC7WV07L6X_F065 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 7WV
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 24mA
- Voltage - Supply:
- 0.9V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-MicroPak
NC7WV07L6X_F065 FAQ
1.How can I place an order for NC7WV07L6X_F065 through Aetrix?
Please submit a Request for Quotation (RFQ) for NC7WV07L6X_F065 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NC7WV07L6X_F065 reliable?
The price and inventory of NC7WV07L6X_F065 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NC7WV07L6X_F065 is usually 5 days.
3.What payment methods are accepted for NC7WV07L6X_F065?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NC7WV07L6X_F065 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NC7WV07L6X_F065?
NC7WV07L6X_F065 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NC7WV07L6X_F065 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NC7WV07L6X_F065?
For technical support, including NC7WV07L6X_F065 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NC7WV07L6X_F065 requirements.
6.How does Aetrix verify that NC7WV07L6X_F065 is sourced from the original manufacturer or authorized distributors?
All NC7WV07L6X_F065 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NC7WV07L6X_F065 meets industry standards.
7.What is the process for return or replacement of NC7WV07L6X_F065?
All NC7WV07L6X_F065 units undergo pre-shipment inspection (PSI). If there is an issue with NC7WV07L6X_F065, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NC7WV07L6X_F065 part is unused and in its original packaging.
Return procedure for NC7WV07L6X_F065:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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