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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi NC7WZ07FHX-L22175

Name: NC7WZ07FHX-L22175
Brand: onsemi
SKU: NC7WZ07FHX-L22175
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: NC7WZ07FHX-L22175

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 6-UFDFN

Datasheet:: NC7WZ07FHX-L22175.pdf

Description:: IC BUFFER NON-INVERT 5.5V 6UDFN

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Product details

Overview

NC7WZ07FHX-L22175 from onsemi is a dual ultra-high-speed CMOS buffer with open-drain outputs, designed for level translation and wired-OR logic in space-constrained systems. It operates across 1.65 V to 5.5 V V_CC, delivers 24 mA I_OL at 3 V, and achieves 2.3 ns typical propagation delay (t_PZL) at 5 V. Used in I²C bus buffering and mixed-voltage interface bridging.

For engineers reviewing the NC7WZ07FHX-L22175 datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain output drive strength, overvoltage-tolerant inputs up to 5.5 V, broad V_CC range compatibility, and MicroPak2™ package footprint constraints.

Technical Context

This device implements two independent non-inverting buffers with open-drain outputs, enabling wired-AND/wired-OR logic and bidirectional level shifting without external pull-ups on the input side. Inputs tolerate 5.5 V regardless of V_CC, supporting 5 V-to-3.3 V or 5 V-to-1.8 V translation.

It features power-down high-impedance I/O states when V_CC = 0 V, proprietary EMI reduction circuitry, and operates from −40 °C to +85 °C. The MicroPak2™-6 package supports fine-pitch PCB assembly with 0.5 mm pitch and 1.0 mm × 1.0 mm body size.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.65 V to 5.5 V - enables single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains
t_PZL (Typ)	2.3 ns at 5 V - supports >200 MHz signal buffering in high-speed digital interfaces
I_OL	±24 mA at 3 V - drives standard 3.3 V I²C bus loads or multiple CMOS inputs without external drivers
Input Voltage Tolerance	Up to 5.5 V independent of V_CC - allows safe interfacing with higher-voltage peripherals without level shifters
Output Type	Open-drain - enables wired-OR bus architectures and bidirectional communication on shared lines
Power-Down Behavior	High-impedance I/O at V_CC = 0 V - prevents back-powering and ensures clean system reset sequencing

Pinout & Package

NC7WZ07FHX-L22175 is packaged in MicroPak2™-6 (UDFN6, 1.0 mm × 1.0 mm, 0.35 mm pitch), a bottom-terminated, leadless package requiring solder paste stencil optimization and X-ray inspection for void control.

Pin/Terminal	Circuit Role	Design Meaning
1	A1	Buffer 1 input - accepts 0–5.5 V logic signals regardless of V_CC voltage
2	GND	Ground reference - must be low-inductance connection to minimize switching noise coupling
3	A2	Buffer 2 input - electrically isolated from A1; supports independent signal routing
4	Y2	Buffer 2 open-drain output - requires external pull-up for logic HIGH; sinks up to 24 mA
5	V_CC	Supply voltage - powers internal logic; decoupling capacitor (100 nF) required within 2 mm
6	Y1	Buffer 1 open-drain output - identical electrical behavior to Y2; supports parallel termination

Key Features

Feature	Design Value
Ultra-High Speed	2.3 ns t_PZL at 5 V enables sub-5 ns round-trip delay in bidirectional bus repeaters
Overvoltage-Tolerant Inputs	5.5 V input rating allows direct connection to 5 V microcontrollers while powered from 1.8 V
Open-Drain Outputs	Supports I²C, SMBus, and PMBus protocols without additional bus transceivers
MicroPak2™ Package	1.0 mm × 1.0 mm footprint reduces PCB area by >60% vs. SC-88, critical for wearables and IoT sensors
Low Static Power	1 µA max ICC at 25 °C minimizes quiescent current in battery-backed subsystems

Applications

I²C Bus Buffering	Mixed-Voltage GPIO Expansion
Use Scenario: Extending I²C bus length beyond 1 m or adding >5 slave devices while maintaining rise time compliance. IC Role / Device Role / Timing Role: Dual open-drain buffer isolating master and slave segments; controls edge rate via external pull-up selection. Use Value: Prevents signal degradation and clock stretching by reducing capacitive loading per segment; maintains 400 kHz timing budget.	Use Scenario: Connecting a 5 V industrial sensor to a 1.8 V microcontroller GPIO bank with level translation. IC Role / Device Role / Timing Role: Input translator and output driver - accepts 5 V sensor output, drives 1.8 V logic input via pull-up to 1.8 V rail. Use Value: Eliminates need for discrete MOSFET translators; preserves 2.3 ns propagation delay for real-time response.
Wired-OR Interrupt Aggregation	Hot-Swap Power Sequencing
Use Scenario: Combining interrupt signals from three peripheral ICs onto a single MCU interrupt line. IC Role / Device Role / Timing Role: Wired-OR logic gate - all inputs tied to separate sources, output pulled up to MCU V_IO. Use Value: Reduces MCU pin count; ensures sub-3 ns interrupt assertion latency with no contention risk.	Use Scenario: Enabling controlled power-up sequencing of FPGA banks where one supply must stabilize before enabling another. IC Role / Device Role / Timing Role: Level-translating enable signal conditioner - converts sequencer's 3.3 V 'ready' flag to 1.2 V enable for LDO. Use Value: Prevents false triggering during brown-out; leverages 0 V power-down state to block enable until V_CC is valid.

I²C Bus Buffering

Mixed-Voltage GPIO Expansion

Use Scenario: Extending I²C bus length beyond 1 m or adding >5 slave devices while maintaining rise time compliance.

IC Role / Device Role / Timing Role: Dual open-drain buffer isolating master and slave segments; controls edge rate via external pull-up selection.

Use Value: Prevents signal degradation and clock stretching by reducing capacitive loading per segment; maintains 400 kHz timing budget.

Use Scenario: Connecting a 5 V industrial sensor to a 1.8 V microcontroller GPIO bank with level translation.

IC Role / Device Role / Timing Role: Input translator and output driver - accepts 5 V sensor output, drives 1.8 V logic input via pull-up to 1.8 V rail.

Use Value: Eliminates need for discrete MOSFET translators; preserves 2.3 ns propagation delay for real-time response.

Wired-OR Interrupt Aggregation

Hot-Swap Power Sequencing

Use Scenario: Combining interrupt signals from three peripheral ICs onto a single MCU interrupt line.

IC Role / Device Role / Timing Role: Wired-OR logic gate - all inputs tied to separate sources, output pulled up to MCU V_IO.

Use Value: Reduces MCU pin count; ensures sub-3 ns interrupt assertion latency with no contention risk.

Use Scenario: Enabling controlled power-up sequencing of FPGA banks where one supply must stabilize before enabling another.

IC Role / Device Role / Timing Role: Level-translating enable signal conditioner - converts sequencer's 3.3 V 'ready' flag to 1.2 V enable for LDO.

Use Value: Prevents false triggering during brown-out; leverages 0 V power-down state to block enable until V_CC is valid.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2G07DCUR	Same 1.65–5.5 V V_CC, but t_PZL = 3.5 ns (typ) at 3.3 V; MicroSM package (1.8 mm × 1.2 mm)	Larger footprint; lower drive (24 mA only at 3.3 V, not guaranteed at 1.8 V)	Preferred when board layout allows larger package and 3.5 ns delay is acceptable
74LVC2G07GM,132	Identical function and speed; XSON6 (1.35 mm × 1.15 mm), 0.5 mm pitch; no overvoltage tolerance (max VIN = V_CC + 0.3 V)	Not suitable for 5 V-to-1.8 V translation; requires strict input voltage limiting	Select only in single-rail systems where all signals stay within V_CC ±0.3 V

Compared with SN74LVC2G07DCUR and 74LVC2G07GM,132, NC7WZ07FHX-L22175 offers superior speed at 5 V, guaranteed 5.5 V input tolerance, and the smallest footprint (1.0 mm × 1.0 mm), making it optimal for high-density, multi-voltage portable designs.

Availability

NC7WZ07FHX-L22175 is available at Aetrix Electronics and suitable for I²C bus extension, mixed-voltage GPIO interfacing, wired-OR interrupt aggregation, and hot-swap power sequencing requiring stable component supply and long-term lifecycle support.

Supply support for NC7WZ07FHX-L22175 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (Nasdaq: ON) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The TinyLogic UHS family, including NC7WZ07FHX-L22175, was engineered for ultra-low-latency, low-power signal conditioning in space-constrained, multi-rail digital systems - especially portable and battery-operated devices.

FAQ

What is the maximum input voltage rating for NC7WZ07FHX-L22175, and does it depend on V_CC?

NC7WZ07FHX-L22175 supports DC input voltages up to 5.5 V regardless of V_CC level - a key feature enabling robust 5 V-to-lower-voltage translation. This overvoltage tolerance is explicitly specified in the Absolute Maximum Ratings table and confirmed in the "Over-Voltage Tolerance Inputs" feature list. The device remains functional and undamaged even when inputs exceed V_CC by up to 3.85 V (e.g., 5.5 V input with V_CC = 1.65 V). This behavior is intrinsic to its input protection structure and applies across the full −40 °C to +85 °C operating range.

Can NC7WZ07FHX-L22175 be used as a level shifter between 5 V and 1.8 V logic domains?

Yes, NC7WZ07FHX-L22175 is specifically designed for this use case. With 5.5 V input tolerance and a minimum V_CC of 1.65 V, it safely accepts 5 V inputs while powered from a 1.8 V rail. Its open-drain outputs require an external pull-up to the destination logic domain (e.g., 1.8 V), enabling bidirectional or unidirectional level translation. The device's VIH/VIL thresholds scale with V_CC, ensuring correct logic interpretation at 1.8 V, and its 2.3 ns propagation delay preserves timing integrity - making NC7WZ07FHX-L22175 ideal for bridging legacy 5 V peripherals to modern low-voltage MCUs.

What is the recommended PCB layout practice for the MicroPak2™-6 package of NC7WZ07FHX-L22175?

For NC7WZ07FHX-L22175 in MicroPak2™-6 (1.0 mm × 1.0 mm, 0.35 mm pitch), use a Type II land pattern per IPC-7351B with 0.25 mm pad width and 0.30 mm solder mask opening. Place a 100 nF ceramic decoupling capacitor between pins 5 (V_CC) and 2 (GND), with vias ≤0.3 mm from pads. Avoid thermal relief on GND - use solid copper pour connected directly to pin 2. Stencil aperture should be 80% of pad area (0.20 mm × 0.20 mm) to prevent bridging. Rely on X-ray inspection post-reflow, as visual inspection of bottom terminations is not feasible.

Does NC7WZ07FHX-L22175 support hot insertion or live-board replacement?

NC7WZ07FHX-L22175 supports partial hot-insertion scenarios due to its power-down high-impedance behavior: when V_CC = 0 V, both inputs and outputs enter high-impedance state, preventing back-driving of live system rails. However, it is not rated for full hot-swap operation (e.g., insertion into a powered-backplane) because absolute maximum ratings do not cover dynamic V_CC ramp-up sequences or simultaneous application of input voltage before V_CC. For true hot-swap applications, external series resistors and slew-rate limiting are recommended. NC7WZ07FHX-L22175's design intent focuses on static multi-rail interfacing, not plug-and-play insertion.

How does the open-drain architecture of NC7WZ07FHX-L22175 affect its use in I²C bus applications?

The open-drain outputs of NC7WZ07FHX-L22175 are essential for I²C compliance: they allow multiple devices to share SDA/SCL lines without contention, enabling wired-AND arbitration. Each buffer output (Y1/Y2) must be pulled up externally - typically to the master's V_IO rail - with resistor values selected per bus capacitance (e.g., 2.2 kΩ for ≤400 pF). Unlike push-pull buffers, NC7WZ07FHX-L22175 avoids bus lockup during arbitration and supports standard I²C rise-time requirements (≤1000 ns at 100 kHz). Its 24 mA sink capability ensures reliable LOW-level drive even under worst-case bus loading.

NC7WZ07FHX-L22175 Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 7WZ

Package/Case:: 6-UFDFN

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 1

Input Type:: -

Output Type:: Open Drain

Current - Output High, Low:: -, 32mA

Voltage - Supply:: 1.65V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-UDFN (1x1)

NC7WZ07FHX-L22175 FAQ

1.How can I place an order for NC7WZ07FHX-L22175 through Aetrix?

Please submit a Request for Quotation (RFQ) for NC7WZ07FHX-L22175 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for NC7WZ07FHX-L22175 reliable?

The price and inventory of NC7WZ07FHX-L22175 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NC7WZ07FHX-L22175 is usually 5 days.

3.What payment methods are accepted for NC7WZ07FHX-L22175?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NC7WZ07FHX-L22175 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for NC7WZ07FHX-L22175?

NC7WZ07FHX-L22175 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your NC7WZ07FHX-L22175 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for NC7WZ07FHX-L22175?

For technical support, including NC7WZ07FHX-L22175 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NC7WZ07FHX-L22175 requirements.

6.How does Aetrix verify that NC7WZ07FHX-L22175 is sourced from the original manufacturer or authorized distributors?

All NC7WZ07FHX-L22175 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NC7WZ07FHX-L22175 meets industry standards.

7.What is the process for return or replacement of NC7WZ07FHX-L22175?

All NC7WZ07FHX-L22175 units undergo pre-shipment inspection (PSI). If there is an issue with NC7WZ07FHX-L22175, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The NC7WZ07FHX-L22175 part is unused and in its original packaging.

Return procedure for NC7WZ07FHX-L22175:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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