Nexperia USA Inc. NCA9595PWJ

Overview

NCA9595PWJ from Nexperia is a low-voltage 16-bit I²C/SMBus GPIO expander with interrupt output, programmable pull-up resistors, and configuration registers. It provides bidirectional I/O expansion across 1.65 V to 5.5 V supply rails, supports up to eight devices on one bus via A0–A2 address pins, delivers 25 mA per output for direct LED drive, and features open-drain active-low INT for event-driven system wake-up in embedded control applications.

For engineers reviewing the NCA9595PWJ datasheet, NCA9595PWJ pinout, NCA9595PWJ application, or NCA9595PWJ equivalent, key selection criteria include its 400 kHz Fast-mode I²C interface, 16 configurable I/Os with polarity inversion and input filtering, power-on reset behavior, Schmitt-triggered SCL/SDA inputs, and 5 V tolerant I/Os enabling mixed-voltage system integration.

Technical Context

The NCA9595PWJ implements an I²C slave architecture with 8-bit register pairs (input/output/polarity/config/pull-up) mapped to two 8-bit ports (P0_0–P0_7 and P1_0–P1_7). Its internal state machine initializes all I/Os as high-impedance inputs at power-on reset, with default pull-ups enabled and polarity inversion disabled.

Interrupt generation is edge-sensitive on input port changes only - outputs cannot trigger INT - and resets upon reading the corresponding input register or when port state reverts. The device uses hardware address pins (A0–A2) to select one of eight possible 7-bit slave addresses (0x20–0x27), with R/W bit determining read/write direction.

Key Specifications

Pinout & Package

TSSOP24 package (SOT355-1), 4.4 mm body width, 0.65 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C GPIO expander applications.

Compared with PCA9555PW and TCA6424APWR, the NCA9595PWJ uniquely combines 5 V tolerant I/O, programmable pull-up disable for ultra-low leakage, and full 1.65–5.5 V operation - making it optimal for heterogeneous voltage domain designs requiring minimal external components and guaranteed industrial temperature stability.

Availability

NCA9595PWJ is available at Aetrix Electronics and suitable for industrial HMIs, multi-sensor hubs, fan control modules, and ACPI power switch controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for NCA9595PWJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions, with manufacturing rooted in process technology leadership and automotive-grade quality standards.

The NCA9595 belongs to Nexperia's I²C GPIO expander product line, engineered specifically for space-constrained embedded systems needing scalable I/O expansion, low-power operation, and robust noise immunity in industrial and computing applications.

FAQ

What is the maximum number of NCA9595PWJ devices that can share one I²C bus?

Up to eight NCA9595PWJ devices can operate on a single I²C bus using hardware address pins A0, A1, and A2. Each combination of HIGH/LOW on these pins selects a unique 7-bit slave address from 0x20 to 0x27. No software configuration or external address decoding is required - address assignment is purely hardware-based and deterministic at power-up.

Can the NCA9595PWJ drive LEDs directly without external current-limiting resistors?

No - external current-limiting resistors are mandatory. Although the NCA9595PWJ supports 25 mA per output, LED forward voltage and desired brightness dictate resistor value. For example, driving a 2 V red LED from 3.3 V requires ~52 Ω for 25 mA. Omitting the resistor risks exceeding absolute maximum ratings and damaging the output FET or LED.

How does the interrupt (INT) pin behave when multiple input pins change simultaneously?

The INT pin asserts once per group of simultaneous input changes and remains active until the host reads the corresponding input port register (00h or 01h). Reading either port clears the interrupt condition for both ports - there is no per-pin interrupt masking. If additional changes occur before the register read, INT stays asserted; no edge is lost, but resolution is port-level, not pin-level.

Is the NCA9595PWJ compatible with SMBus Alert Response Protocol (ARP)?

No - the NCA9595PWJ does not implement SMBus ARP. Its INT pin is a simple open-drain active-low signal indicating *any* input port change. SMBus ARP requires dynamic slave address claiming and protocol-level handshake, which this device lacks. Use standard I²C polling or INT-driven register reads instead for status monitoring.