onsemi NCP120AMX105TCG
- Part No.:
- NCP120AMX105TCG
- Manufacturer:
- onsemi
- Package:
- 6-XFDFN Exposed Pad
- Datasheet:
-
NCP120AMX105TCG.pdf
- Description:
- IC REG LINEAR 1.05V 150MA 6XDFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,873
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Product details
Overview
NCP120AMX105TCG from onsemi is a 150 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering a fixed 1.05 V output at up to 150 mA. It features 75 mV max dropout at full load, ±1.5% output accuracy over −40°C to +85°C, and ultra-low bias current (80 µA typ), making it suitable for noise-sensitive, space-constrained portable power rails such as smartphone core I/O supplies.
For engineers reviewing the NCP120AMX105TCG datasheet, pinout, applications, or equivalent options, key selection criteria include its dual-rail architecture (VIN/VBIAS), active output discharge capability, XDFN6 1.2 mm × 1.2 mm package, and PSRR of 80 dB (VBIAS-to-VOUT at 1 kHz), critical for post-regulation in battery-powered SoC subsystems.
Technical Context
The NCP120AMX105TCG implements a dual-input VLDO architecture: VIN powers the NMOS pass element while VBIAS (2.4–5.5 V) independently supplies internal control circuitry, decoupling regulation stability from input rail noise. Its enable pin includes hysteresis, and thermal shutdown activates at 160°C with 20°C hysteresis.
It supports stable operation with only 1 µF ceramic output capacitance and integrates active output discharge (enabled in "A"-suffix variants), ensuring rapid VOUT discharge during shutdown. Dropout is defined separately for VIN–VOUT (75 mV max) and VBIAS–VOUT (1.4 V max), both characterized across temperature and load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.05 V - precisely regulated for low-voltage I/O domains like LPDDR interfaces or sensor analog front-ends. |
| Max Output Current | 150 mA - sufficient for powering small logic blocks or peripheral controllers without external boost. |
| VIN Dropout Voltage | 75 mV max at 150 mA - enables regulation from inputs as low as 1.125 V, ideal for single-cell Li-ion post-regulation. |
| VBIAS Range | 2.4 V to 5.5 V - allows use of higher-stability rails (e.g., main PMIC outputs) to isolate control circuitry from noisy VIN. |
| PSRR (VBIAS-to-VOUT) | 80 dB at 1 kHz - suppresses bias rail noise before it modulates output, critical for RF or ADC reference supplies. |
| Output Accuracy | ±1.5% over −40°C to +85°C - ensures timing margin compliance in digital I/O voltage domains. |
| Enable Threshold | VEN(H) = 0.9 V, VEN(L) = 0.4 V - compatible with 1.2 V or 1.8 V GPIO logic without level-shifting. |
Pinout & Package
XDFN6 package (Case 711AT), 1.2 mm × 1.2 mm × 0.4 mm, with exposed thermal pad soldered to ground plane for optimal thermal performance (RJA = 170°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output | Delivers stable 1.05 V; connects directly to load with minimal trace inductance for noise control. |
| 2 - N/C | No connect | Not internally bonded; must remain unconnected per design - no routing or stitching allowed. |
| 3 - EN | Logic-enable input | Active-high control: ≥0.9 V enables regulator; ≤0.4 V disables with 0.5 µA bias current in shutdown. |
| 4 - BIAS | Bias supply input | Powers internal reference and control circuits; requires ≥2.4 V and stable decoupling (≥0.1 µF). |
| 5 - GND | Ground reference | Common return for IN, OUT, BIAS, and EN; thermal pad must be soldered to PCB ground plane. |
| 6 - IN | Main input supply | Feeds NMOS pass transistor; operates down to VOUT + 75 mV, enabling ultra-low VIN applications. |
Key Features
| Feature | Design Value |
|---|---|
| Active output discharge | Integrated 150 Ω pull-down (NCP120A variant only) discharges VOUT rapidly after EN deactivation - prevents floating states in sequenced power systems. |
| Dual-rail architecture | Separate VIN and VBIAS inputs isolate noise-sensitive control circuitry from noisy main supply - improves PSRR and transient immunity. |
| Ultra-low bias current | 80 µA typical operating current from VBIAS - extends battery life in always-on monitoring circuits without sacrificing regulation speed. |
| Stable with 1 µF ceramic | No external compensation required; supports compact, low-ESR ceramic capacitors - reduces BOM count and board area in mobile designs. |
| Thermal shutdown protection | 160°C trip with 20°C hysteresis - autonomously disables output under overload or poor heatsinking, preventing permanent damage. |
Applications
| Smartphone I/O Rail Regulation | Low-Power Camera Sensor Bias |
|---|---|
Use Scenario: Regulating 1.05 V supply for LPDDR4/5 I/O buffers in smartphones where VIN varies between 1.2 V and 1.8 V from intermediate buck converters. IC Role / Device Role / Timing Role: Post-regulator providing precise, low-noise voltage to memory interface I/O banks, ensuring signal integrity and timing margin. Use Value: 75 mV dropout enables regulation from lowest VIN (1.125 V), while 80 dB VBIAS PSRR rejects noise from shared PMIC bias rails. |
Use Scenario: Powering image sensor analog front-end (AFE) and timing controller requiring clean, fast-turn-on 1.05 V supply during burst capture mode. IC Role / Device Role / Timing Role: Low-noise linear regulator supplying bias to sensor pixel array and column ADC reference, minimizing quantization noise. Use Value: 40 µVRMS output noise (10 Hz–100 kHz) and monotonic start-up prevent image artifacts; active discharge clears residual charge before next frame. |
| Wearable BLE SoC Core Supply | Industrial IoT Edge Node MCU I/O |
Use Scenario: Delivering 1.05 V to Bluetooth LE radio transceiver I/O pins in coin-cell–powered wearables where quiescent current directly impacts battery life. IC Role / Device Role / Timing Role: Ultra-low-IQ LDO supplying regulated voltage to RF interface logic, synchronized with radio wake/sleep cycles via EN pin. Use Value: 0.5 µA disable current and 150 µs turn-on time support aggressive duty cycling without voltage droop or startup delay. |
Use Scenario: Providing isolated 1.05 V rail for industrial microcontroller GPIO banks interfacing with 1.2 V logic sensors in electrically noisy factory environments. IC Role / Device Role / Timing Role: Noise-immune post-regulator decoupling MCU I/O from main 3.3 V system rail, improving ESD robustness and signal fidelity. Use Value: Dual-rail architecture rejects coupled noise from shared 3.3 V supply; ±1.5% accuracy ensures reliable level translation across temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-dropout voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B105MR-G | Single-rail (VIN-only) 150 mA LDO; no VBIAS input; 100 mV dropout at 150 mA; no active discharge. | Lacks VBIAS isolation - less effective in high-PSRR, multi-rail noise-sensitive systems. | Choose when board space permits larger dropout margin and bias rail noise is not a concern. |
| Richtek RT9080L-105GJ5 | Single-rail 200 mA LDO; 60 mV dropout; integrated soft-start; no active discharge; different pinout (SOT-23-5). | Higher current but no VBIAS separation - unsuitable for applications requiring independent bias rail control. | Prefer when higher output current is needed and thermal constraints allow SOT-23-5 footprint. |
Compared with Torex XC6210B105MR-G and Richtek RT9080L-105GJ5, the NCP120AMX105TCG uniquely provides dual-rail operation and active discharge in a 1.2 mm × 1.2 mm XDFN6 package - essential for miniaturized, noise-critical portable designs requiring precise sequencing and rail isolation.
Availability
NCP120AMX105TCG is available at Aetrix Electronics and suitable for smartphone I/O regulation, wearable BLE SoC power, camera sensor biasing, and industrial IoT edge node MCU I/O requiring stable component supply with guaranteed long-term availability.
Supply support for NCP120AMX105TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, delivering silicon solutions for automotive, industrial, cloud, and intelligent devices.
The NCP120AMX105TCG belongs to onsemi's precision low-dropout regulator product line, engineered specifically for space-constrained, noise-sensitive portable applications requiring dual-rail architecture and ultra-low quiescent current.
FAQ
What is the maximum input voltage for the NCP120AMX105TCG?
The NCP120AMX105TCG supports an absolute maximum input voltage (VIN) of 6 V. Its recommended operating VIN range is from VOUT + VDO (i.e., ≥1.125 V) up to 5.5 V. Exceeding 6 V risks permanent damage per the Absolute Maximum Ratings table in the datasheet.
Does the NCP120AMX105TCG require an external capacitor on the BIAS pin?
Yes - the NCP120AMX105TCG requires a minimum 0.1 µF ceramic capacitor between BIAS and GND, placed as close as possible to the pin. This stabilizes the internal control circuitry powered by VBIAS and prevents oscillation or erratic enable behavior under dynamic load conditions.
Is active output discharge enabled by default on the NCP120AMX105TCG?
Yes - the "A" suffix in NCP120AMX105TCG explicitly denotes the active discharge variant. When EN is driven low, an internal 150 Ω pull-down connects OUT to GND, discharging the output capacitor rapidly. This feature is absent in "B"-suffix variants.
Can the NCP120AMX105TCG operate with only the VIN pin powered and VBIAS left unconnected?
No - the NCP120AMX105TCG requires both VIN and VBIAS to be within specification (VBIAS ≥2.4 V) for normal operation. Leaving VBIAS unconnected or below UVLO threshold (≈2.2 V) triggers undervoltage lockout, disabling regulation regardless of VIN or EN state.
What is the thermal resistance (RJA) of the NCP120AMX105TCG in its XDFN6 package?
The NCP120AMX105TCG in the XDFN6 (Case 711AT) package has a junction-to-air thermal resistance (RJA) of 170°C/W, measured with the thermal pad soldered to a standard 1-in² copper pour on the PCB. Performance improves significantly with enhanced thermal vias and multilayer ground planes.
NCP120AMX105TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.05V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.075V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 80dB ~ 70dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XDFN (1.2x1.2)
NCP120AMX105TCG FAQ
1.How can I place an order for NCP120AMX105TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP120AMX105TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP120AMX105TCG reliable?
The price and inventory of NCP120AMX105TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP120AMX105TCG is usually 5 days.
3.What payment methods are accepted for NCP120AMX105TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP120AMX105TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP120AMX105TCG?
NCP120AMX105TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP120AMX105TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP120AMX105TCG?
For technical support, including NCP120AMX105TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP120AMX105TCG requirements.
6.How does Aetrix verify that NCP120AMX105TCG is sourced from the original manufacturer or authorized distributors?
All NCP120AMX105TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP120AMX105TCG meets industry standards.
7.What is the process for return or replacement of NCP120AMX105TCG?
All NCP120AMX105TCG units undergo pre-shipment inspection (PSI). If there is an issue with NCP120AMX105TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP120AMX105TCG part is unused and in its original packaging.
Return procedure for NCP120AMX105TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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