onsemi NCP133AMX110TCG
- Part No.:
- NCP133AMX110TCG
- Manufacturer:
- onsemi
- Package:
- 6-XFDFN Exposed Pad
- Datasheet:
-
NCP133AMX110TCG.pdf
- Description:
- IC REG LINEAR 1.1V 500MA 6XDFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,071
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Product details
Overview
NCP133AMX110TCG from onsemi is a 500 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering 1.10 V output with ±1.5% accuracy over temperature and ultra-low 140 mV dropout at full load-designed for noise-sensitive, space-constrained portable applications such as smartphone core logic rails and camera sensor biasing.
For engineers reviewing the NCP133AMX110TCG datasheet, pinout, applications, or equivalent options, this page provides verified technical context, fixed-output configuration details, active discharge capability, thermal shutdown behavior, and real-world design implications for battery-powered DC/DC post-regulation.
Technical Context
The NCP133AMX110TCG implements a dual-rail architecture: VIN supplies the NMOS pass element while VBIAS powers internal control circuitry-including reference, error amplifier, and enable logic-enabling stable regulation even when VIN approaches VOUT. Its VBIAS input requires ≥2.4 V and supports up to 5.5 V, with UVLO hysteresis of 0.2 V.
It features an integrated active output discharge path activated during shutdown (VEN ≤ 0.4 V), pulling VOUT to GND via a 150 Ω internal FET; this prevents floating outputs in multi-rail systems. Thermal shutdown triggers at +160°C (rising) and releases at +140°C (falling), with RthJCb = 33°C/W enabling robust thermal performance in XDFN6 packages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.10 V - no external resistors required; optimized for low-voltage processor I/O or memory interface rails. |
| Max Output Current | 500 mA - supports moderate-power digital loads without external current boosting. |
| Dropout Voltage | 140 mV typ. at 500 mA - enables operation with VIN as low as 1.24 V, critical for single-cell Li-ion or Li-poly systems. |
| Output Accuracy | ±1.5% over −40°C to +85°C - ensures reliable voltage margining for 1.1 V logic domains across industrial temperature range. |
| Bias Supply Current | 80 µA typ. at 2.7 V - minimizes auxiliary rail loading in battery-critical applications. |
| PSRR @ 1 kHz | 70 dB (VIN-to-VOUT), 80 dB (VBIAS-to-VOUT) - suppresses switching noise from upstream DC/DC converters feeding VIN or VBIAS. |
| Enable Threshold | VEN(H) = 0.9 V, VEN(L) = 0.4 V - compatible with standard 1.2 V or 1.8 V GPIOs without level-shifting. |
| Stability | Stable with 2.2 µF ceramic output capacitor - eliminates need for large tantalum or electrolytic capacitors in compact layouts. |
Pinout & Package
XDFN6 package (Case 711AT), 1.2 mm × 1.2 mm × 0.4 mm, thermally enhanced with exposed pad soldered to ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output | Delivers 1.10 V to load; connects directly to decoupling capacitor and load; internal active discharge path engages here during shutdown. |
| 2 - N/C | No connect | True no-connect; PCB trace routing permitted but must not be bonded or tied to any net. |
| 3 - EN | Logic-level enable | Active-high control: ≥0.9 V enables regulation; ≤0.4 V disables output and activates discharge; internal pull-down not present. |
| 4 - BIAS | Bias supply input | Powers internal reference and control circuits; must be ≥2.4 V; monitored by UVLO; contributes to PSRR performance. |
| 5 - GND | Ground reference | Analog and power ground common point; exposed pad must be soldered to PCB ground plane for thermal and EMI integrity. |
| 6 - IN | Main input supply | Feeds NMOS pass transistor; dropout defined relative to OUT; accepts 0.8–5.5 V, but regulated output only possible when VIN ≥ VOUT + VDO. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dropout | 140 mV at 500 mA enables use with sub-1.25 V input sources-critical for extending battery runtime in portable devices. |
| Separate VBIAS rail | Decouples control circuitry from noisy main input, improving PSRR and allowing independent optimization of bias supply stability and noise filtering. |
| Active output discharge | 150 Ω internal pull-down discharges VOUT within microseconds upon disable-prevents unintended logic states in multi-supply SoC interfaces. |
| Low quiescent current | 80 µA typical bias current and 0.5 µA in shutdown minimize parasitic drain on battery or standby rails. |
| Thermal protection | Auto-recovering shutdown at +160°C / +140°C hysteresis prevents permanent damage during transient overload or poor heatsinking. |
| Small-footprint packaging | XDFN6 (1.2 mm × 1.2 mm) reduces board area by >60% vs. SOT-23, supporting high-density mobile and wearable PCB designs. |
Applications
| Smartphone Application Processor Core Rail | Camera Sensor Bias Supply |
|---|---|
|
Use Scenario: Powering ARM Cortex-A series CPU cores requiring tightly regulated 1.10 V at up to 500 mA during burst-mode operation. IC Role / Device Role / Timing Role: Post-regulator after buck converter; provides low-noise, fast-transient response voltage for digital logic with monotonic startup. Use Value: 40 µVRMS output noise and 150 µs turn-on time ensure clean power delivery during DVFS transitions without glitching or reset events. |
Use Scenario: Supplying analog front-end and image signal processor (ISP) bias voltage in compact mobile cameras. IC Role / Device Role / Timing Role: Low-noise linear regulator for precision analog blocks; active discharge prevents residual charge from corrupting next-frame exposure timing. Use Value: 80 dB VBIAS-to-VOUT PSRR rejects noise from shared PMIC bias rails, preserving dynamic range and SNR in 12-bit+ image capture. |
| Tablet SoC I/O Voltage Domain | DVR Memory Interface Regulator |
|
Use Scenario: Delivering 1.10 V to LPDDR4/LPDDR5 I/O buffers in tablets where space and thermal headroom are constrained. IC Role / Device Role / Timing Role: Point-of-load regulator placed adjacent to memory controller; handles pulsed current demands up to 500 mA with minimal voltage droop. Use Value: 140 mV dropout allows operation from 1.24 V intermediate rail, reducing conduction loss and heat generation versus higher-dropout alternatives. |
Use Scenario: Regulating 1.10 V for DDR memory termination and command/address buffers in digital video recorders. IC Role / Device Role / Timing Role: Stable, low-ESR supply ensuring signal integrity on high-speed memory buses; enabled/disabled synchronously with system sleep/wake. Use Value: Active discharge clears VOUT within 10 µs of disable, eliminating hold-up time that could cause bus contention or data corruption during power sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-dropout, fixed-output voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A05115PYKAR | 300 mA max output, 170 mV dropout at 300 mA, no VBIAS rail, 1.15 V fixed output. | Lacks separate bias supply; lower current rating limits use in high-pulse-load scenarios like CPU burst mode. | Select if board space allows larger YKA package and application does not require >300 mA or dual-rail noise isolation. |
| MCP1826T-1102E/DB | 500 mA, 250 mV dropout at 500 mA, no active discharge, 1.10 V fixed output, SOT-23-5 package. | Higher dropout increases minimum input requirement to 1.35 V; no output discharge risks floating nodes in multi-rail sequencing. | Choose only if cost sensitivity outweighs thermal and sequencing requirements, and layout accommodates larger SOT-23 footprint. |
Compared with TPS7A05115PYKAR and MCP1826T-1102E/DB, the NCP133AMX110TCG uniquely combines 500 mA capability, 140 mV dropout, active discharge, and VBIAS isolation-making it optimal for thermally dense, noise-sensitive, and tightly sequenced portable SoC power domains.
Availability
NCP133AMX110TCG is available at Aetrix Electronics and suitable for smartphone processor core rails, camera sensor biasing, tablet SoC I/O domains, and DVR memory interface regulation requiring stable component supply with guaranteed long-term continuity.
Supply support for NCP133AMX110TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP133AMX110TCG belongs to onsemi's VLDO regulator product line, engineered specifically for ultra-low-noise, space-constrained battery-powered applications demanding precise voltage regulation and fast transient response.
FAQ
What is the minimum input voltage required for NCP133AMX110TCG to regulate 1.10 V output?
The NCP133AMX110TCG requires VIN ≥ VOUT + VDO. With a typical dropout voltage of 140 mV at 500 mA, the minimum functional VIN is 1.24 V. At lighter loads (e.g., 150 mA), dropout drops to 75 mV, allowing operation down to 1.175 V-enabling compatibility with single-cell Li-ion batteries under discharge.
Does NCP133AMX110TCG require an external resistor network to set its output voltage?
No. The NCP133AMX110TCG is a fixed-output variant delivering precisely 1.10 V without external feedback components. Pin 2 is marked N/C (no connect), confirming no adjustment capability-unlike the ADJ version (NCP133AMXADJTCG) which requires R1/R2 resistors per the formula VOUT = 0.8 V × (1 + R1/R2).
How does the active output discharge function operate in NCP133AMX110TCG?
The NCP133AMX110TCG integrates an internal 150 Ω pull-down FET between OUT and GND, activated automatically when EN is driven ≤0.4 V. This discharges the output capacitor rapidly-typically within 10 µs for a 2.2 µF load-ensuring clean power-down sequencing and preventing unintended logic states in downstream ICs.
Can NCP133AMX110TCG be used with only one supply rail instead of separate VIN and VBIAS?
Yes-but with constraints. If VIN and VBIAS are tied together, the combined rail must meet both requirements: ≥2.4 V (for VBIAS UVLO) and ≥VOUT + VDO (for regulation). For 1.10 V output, minimum joint supply is ~1.24 V, but VBIAS dropout (1.1–1.5 V) becomes limiting-so a joint 2.7 V rail is recommended for guaranteed performance and PSRR benefits.
What thermal derating applies to NCP133AMX110TCG at 500 mA continuous load?
With RthJCb = 33°C/W and maximum junction temperature of 150°C, the NCP133AMX110TCG dissipates (1.24 V – 1.10 V) × 0.5 A = 70 mW at minimum VIN. Ambient temperature can reach +127°C before hitting TJ(max), assuming ideal board-level heatsinking. In typical 4-layer PCBs with 1-in² copper pour, safe continuous 500 mA operation is sustained up to +85°C ambient.
NCP133AMX110TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.1V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 500mA
- Current - Output:
- 500mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 80dB ~ 70dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XDFN (1.2x1.2)
NCP133AMX110TCG FAQ
1.How can I place an order for NCP133AMX110TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP133AMX110TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP133AMX110TCG reliable?
The price and inventory of NCP133AMX110TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP133AMX110TCG is usually 5 days.
3.What payment methods are accepted for NCP133AMX110TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP133AMX110TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP133AMX110TCG?
NCP133AMX110TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP133AMX110TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP133AMX110TCG?
For technical support, including NCP133AMX110TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP133AMX110TCG requirements.
6.How does Aetrix verify that NCP133AMX110TCG is sourced from the original manufacturer or authorized distributors?
All NCP133AMX110TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP133AMX110TCG meets industry standards.
7.What is the process for return or replacement of NCP133AMX110TCG?
All NCP133AMX110TCG units undergo pre-shipment inspection (PSI). If there is an issue with NCP133AMX110TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP133AMX110TCG part is unused and in its original packaging.
Return procedure for NCP133AMX110TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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