My Inquiry
My Account
onsemi NCP133BMXADJTCG
- Part No.:
- NCP133BMXADJTCG
- Manufacturer:
- onsemi
- Package:
- 6-XFDFN Exposed Pad
- Datasheet:
-
NCP133BMXADJTCG.pdf
- Description:
- IC REG LIN POS ADJ 500MA 6XDFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,920
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP133BMXADJTCG from onsemi is a 500 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering adjustable output from 0.8 V to 3.6 V with ±1.5% accuracy over temperature and ultra-low 140 mV dropout at full load. It targets space-constrained, noise-sensitive portable applications including smartphone core logic rails and camera sensor biasing.
For engineers reviewing the NCP133BMXADJTCG datasheet, pinout, applications, or equivalent options, key selection criteria include its dual-rail architecture (VIN + VBIAS), active discharge absence, XDFN6 1.2 mm × 1.2 mm footprint, and compatibility with 2.2 µF ceramic output capacitors in battery-powered DC/DC post-regulation.
Technical Context
The NCP133BMXADJTCG employs an NMOS pass transistor powered by VIN while internal control circuitry draws from VBIAS (2.4–5.5 V), enabling stable regulation even when VIN approaches VOUT. Its adjustable version uses an external resistor divider on the ADJ pin to set output voltage with 0.8 V reference precision.
Unlike PMOS LDOs, this architecture decouples loop stability from output capacitor ESR and supports monotonic startup with controlled inrush current. Thermal shutdown activates at 160°C and recovers at 140°C, and UVLO on VBIAS ensures operation only above 2.4 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 500 mA max - supports high-current digital loads like application processors or image signal processors without thermal derating under typical PCB layout. |
| VIN Dropout Voltage | 140 mV typ. at 500 mA - enables regulation from input as low as VOUT + 0.14 V, critical for Li-ion battery discharge down to 3.0 V. |
| VBIAS Range | 2.4 V to 5.5 V - allows use of dedicated bias rail (e.g., 3.3 V or 5 V system rail) independent of main input, improving PSRR and noise rejection. |
| Output Accuracy | ±1.5% over −40°C to +85°C - ensures reliable voltage margining for sub-1 V core supplies in mobile SoCs. |
| PSRR (VBIAS) | 80 dB at 1 kHz - suppresses noise coupling from shared bias rails into sensitive analog or RF subsystems. |
| Enable Threshold | VEN(H) = 0.9 V, VEN(L) = 0.4 V - compatible with standard 1.8 V or 3.3 V GPIOs for precise ON/OFF sequencing in multi-rail power systems. |
| Output Noise | 50 × VOUT µVRMS (10 Hz–100 kHz) - low enough for powering PLLs, ADCs, or camera sensors without added filtering. |
| Package | XDFN6 1.2 mm × 1.2 mm × 0.4 mm - 0.4 mm profile and 0.4 mm pitch enable ultra-thin mobile PCB stacking with minimal board area. |
Pinout & Package
Package: XDFN6 (Case 711AT), 1.2 mm × 1.2 mm × 0.4 mm, thermally enhanced bottom-exposed pad soldered to ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers stable, low-noise VOUT; connects directly to load with minimal trace inductance to preserve transient response. |
| 2 - ADJ | Feedback input for adjustable output | Accepts resistor divider midpoint; sets VOUT = 0.8 V × (1 + R1/R2); requires ≤100 kΩ total resistance for accuracy. |
| 3 - EN | Logic-level enable control | Active-high input; internal hysteresis prevents chatter during slow-rising control signals; pulls down to GND when disabled. |
| 4 - BIAS | Dedicated bias supply for internal circuitry | Must be ≥2.4 V; powers reference, error amp, and control logic independently of VIN - improves PSRR and line regulation. |
| 5 - GND | Analog and power ground reference | Common return for IN, OUT, BIAS, and EN; bottom thermal pad must be soldered to PCB ground plane for RthJCb = 33°C/W. |
| 6 - IN | Main input voltage supply | Feeds NMOS pass transistor; dropout defined relative to VOUT; requires 1 µF ceramic bypass near pin. |
Key Features
| Feature | Design Value |
|---|---|
| Separate VBIAS rail | Enables >70 dB PSRR from bias source and eliminates VIN ripple coupling into regulated output - essential for mixed-signal SoC power domains. |
| Ultra-low 140 mV dropout | Extends usable battery life by allowing regulation down to ~2.85 V on a 3.0 V nominal Li-ion cell, preserving system runtime during deep discharge. |
| Stable with 2.2 µF ceramic cap | Eliminates need for large tantalum or aluminum electrolytics - reduces BOM cost, size, and failure risk in portable designs. |
| Monotonic startup | Controls slew rate of VOUT rise to limit inrush current into downstream capacitance - prevents brownout of shared supply rails. |
| Thermal shutdown with hysteresis | Shuts down at 160°C and re-enables at 140°C - protects against sustained overload or poor heatsinking without requiring external reset circuitry. |
| No active output discharge | Unlike NCP133A variants, NCP133B omits internal discharge FET - preserves charge on output caps during disable, simplifying power sequencing in multi-rail systems. |
Applications
| Smartphone Core Logic Rail | Camera Sensor Bias Supply |
|---|---|
|
Use Scenario: Powering ARM Cortex-A series CPU cores operating at 0.8–1.2 V with dynamic DVFS voltage scaling. IC Role / Device Role / Timing Role: Post-regulator after buck converter, providing final low-noise, tightly regulated voltage with fast transient response. Use Value: Maintains ±1.5% output accuracy across temperature and load, ensuring reliable processor operation while minimizing margining overhead. |
Use Scenario: Supplying analog front-end and pixel array bias for high-resolution CMOS image sensors in smartphones. IC Role / Device Role / Timing Role: Low-noise, low-dropout linear regulator isolating sensor analog supply from noisy digital domains. Use Value: 50 × VOUT µVRMS noise and 80 dB VBIAS PSRR prevent image artifacts caused by switching noise coupling from adjacent power rails. |
| Tablet Application Processor I/O | Portable DVR Memory Interface |
|
Use Scenario: Delivering 1.8 V or 2.5 V to LPDDR4/5 I/O banks with tight voltage tolerance and low EMI. IC Role / Device Role / Timing Role: Dedicated LDO for memory interface power domain, decoupled from main SoC core supply. Use Value: Dual-rail architecture (VIN + VBIAS) rejects noise from shared system rails, improving signal integrity and timing margin on high-speed data buses. |
Use Scenario: Regulating 1.2 V DDR memory termination voltage (VTT) in compact DVR modules with limited PCB area. IC Role / Device Role / Timing Role: Compact, low-profile LDO replacing larger solutions to meet strict height constraints in fanless enclosures. Use Value: XDFN6 1.2 mm × 1.2 mm package fits within dense BGA escape routing zones, enabling direct placement beneath memory packages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar very low dropout voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NCP133AMXADJTCG | Includes active output discharge FET; otherwise identical electrical specs and pinout. | Required where rapid VOUT discharge is needed during power-down sequencing (e.g., FPGA configuration rails). | Select NCP133AMXADJTCG if active discharge is mandatory; NCP133BMXADJTCG is preferred when output hold-up is desired. |
| TPL7407LDR | 7-channel 500 mA NMOS LDO with integrated enable and thermal protection; fixed 3.3 V/5 V outputs only, no adjustable version. | Suitable for multi-rail systems needing consolidated regulation but lacks programmability and dual-rail architecture. | Choose TPL7407LDR for space-constrained multi-output designs where fixed voltages suffice and VBIAS independence is not required. |
Compared with NCP133AMXADJTCG, the NCP133BMXADJTCG saves board area by omitting discharge circuitry and avoids unintended discharge of downstream capacitance; versus TPL7407LDR, it offers superior noise performance, adjustable output, and independent VBIAS for higher PSRR - making it optimal for single-rail, precision analog or low-voltage digital loads.
Availability
NCP133BMXADJTCG is available at Aetrix Electronics and suitable for smartphone core logic rails, camera sensor bias supplies, tablet I/O domains, portable DVR memory interfaces, and other applications requiring stable component supply with guaranteed long-term availability.
Supply support for NCP133BMXADJTCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP133 family is designed for ultra-low-noise, ultra-low-dropout regulation in battery-powered portable electronics - prioritizing small footprint, low IQ, and dual-rail flexibility for next-generation mobile SoC power architectures.
FAQ
What is the minimum VBIAS voltage required for NCP133BMXADJTCG to operate?
The NCP133BMXADJTCG requires VBIAS ≥ 2.4 V to enable internal circuitry and maintain regulation. Below this threshold, the device enters undervoltage lockout (UVLO) and disables output regardless of EN state. The UVLO hysteresis is 0.2 V, so VBIAS must rise above 2.6 V to re-enable operation after dropout.
Can NCP133BMXADJTCG be used with only VIN and no separate VBIAS supply?
No - the NCP133BMXADJTCG requires both VIN and VBIAS to function. VBIAS powers the internal reference, error amplifier, and control logic; omitting it prevents regulation. If a single supply is mandatory, consider fixed-output alternatives like NCP133BMX120TCG, but VBIAS remains required.
What is the maximum output voltage achievable with NCP133BMXADJTCG?
The NCP133BMXADJTCG supports adjustable output up to 3.6 V, set via external resistors on the ADJ pin using VOUT = 0.8 V × (1 + R1/R2). This upper limit is specified in the datasheet and validated across temperature and load conditions - exceeding it risks instability or specification violation.
Does NCP133BMXADJTCG include active output discharge functionality?
No - the "B" suffix in NCP133BMXADJTCG explicitly denotes the non-active-discharge variant. Unlike the "A"-suffix NCP133AMXADJTCG, it lacks the internal discharge FET. When disabled, the output remains floating or holds voltage depending on external load and capacitance.
What ceramic capacitor value is recommended for stable operation of NCP133BMXADJTCG?
A 2.2 µF ceramic capacitor is the minimum recommended effective output capacitance for stable operation of NCP133BMXADJTCG. The device is characterized and guaranteed stable across 2.2 µF to 10 µF, and multiple parallel ceramics are acceptable as long as total effective capacitance falls within that range.
NCP133BMXADJTCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 3.6V
- Voltage Dropout (Max):
- 0.25V @ 500mA
- Current - Output:
- 500mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 80dB ~ 70dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XDFN (1.2x1.2)
NCP133BMXADJTCG FAQ
1.How can I place an order for NCP133BMXADJTCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP133BMXADJTCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP133BMXADJTCG reliable?
The price and inventory of NCP133BMXADJTCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP133BMXADJTCG is usually 5 days.
3.What payment methods are accepted for NCP133BMXADJTCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP133BMXADJTCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP133BMXADJTCG?
NCP133BMXADJTCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP133BMXADJTCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP133BMXADJTCG?
For technical support, including NCP133BMXADJTCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP133BMXADJTCG requirements.
6.How does Aetrix verify that NCP133BMXADJTCG is sourced from the original manufacturer or authorized distributors?
All NCP133BMXADJTCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP133BMXADJTCG meets industry standards.
7.What is the process for return or replacement of NCP133BMXADJTCG?
All NCP133BMXADJTCG units undergo pre-shipment inspection (PSI). If there is an issue with NCP133BMXADJTCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP133BMXADJTCG part is unused and in its original packaging.
Return procedure for NCP133BMXADJTCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP133BMXADJTCG Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
