onsemi NCP139AFCT180T2G
- Part No.:
- NCP139AFCT180T2G
- Manufacturer:
- onsemi
- Package:
- 6-XFBGA, WLCSP
- Datasheet:
-
NCP139AFCT180T2G.pdf
- Description:
- IC REG LINEAR 1.8V 1A 6WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,089
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP139AFCT180T2G from onsemi is a 1 A very low dropout (VLDO) linear regulator with NMOS pass transistor and separate bias rail (VBIAS), delivering ±1% output voltage accuracy over temperature and ultra-low 50 mV dropout at 1 A load. It features logic-level enable control, active output discharge, and stable operation with 10 µF ceramic output capacitors - designed for noise-sensitive, space-constrained portable applications such as smartphone core voltage rails.
For engineers reviewing the NCP139AFCT180T2G datasheet, pinout, applications, or equivalent options, key selection criteria include its fixed 1.8 V output, dual-rail architecture (VIN + VBIAS), thermal shutdown threshold (160°C), PSRR of 75 dB (VIN) and 85 dB (VBIAS) at 1 kHz, and WLCSP6 package compatibility with high-density PCB layouts.
Technical Context
The NCP139AFCT180T2G implements a dual-supply NMOS-based VLDO architecture where VIN supplies the power path and VBIAS (3.0–5.5 V) powers internal control circuitry independently - enabling optimized efficiency and stability in battery-powered systems. Its bias-input current is typ. 35 µA under load and drops to 0.5 µA in shutdown, supporting ultra-low quiescent power design.
Unlike PMOS LDOs, the NMOS topology decouples loop stability from output capacitor ESR, allowing robust performance with small 10 µF ceramic capacitors. The device integrates undervoltage lockout (UVLO) on VBIAS with 1.6 V threshold and 0.2 V hysteresis, plus monotonic startup and thermal shutdown (160°C activation / 140°C recovery) for system reliability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.8 V - eliminates external feedback resistors and reduces BOM count for dedicated core supply rails. |
| Max Output Current | 1.0 A continuous, 1.3 A peak - supports transient loads in processor I/O or memory subsystems without derating. |
| VIN Dropout Voltage | Typ. 50 mV at 1 A - enables operation with minimal headroom (e.g., 1.85 V input for 1.8 V output), extending battery runtime. |
| VBIAS Range | 3.0 V to 5.5 V - allows flexible bias sourcing from auxiliary rails or regulated system supplies independent of VIN. |
| Output Accuracy | ±1.0% over −40°C to +85°C - ensures consistent voltage delivery across industrial temperature range without calibration. |
| PSRR (VIN) | 75 dB at 1 kHz - suppresses switching noise from upstream DC/DC converters feeding VIN, critical for RF or analog subsystems. |
| PSRR (VBIAS) | 85 dB at 1 kHz - isolates sensitive control circuitry from bias rail noise, improving regulation stability. |
| Thermal Shutdown | 160°C activation - protects against sustained overload or poor heatsinking in compact WLCSP6 footprint. |
Pinout & Package
Package: WLCSP6 (1.2 mm × 0.8 mm, 0.4 mm pitch, Case 567MV) - ultra-compact chip-scale package optimized for high-density mobile PCBs with minimal board area and thermal resistance (RJA = 69°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT | Regulated output voltage node | Delivers stable 1.8 V to load; requires direct connection to 10 µF ceramic capacitor with low-impedance PCB copper pour. |
| VIN | Main power input | Accepts 1.8 V to 5.5 V input; dropout behavior defined relative to VOUT; must be ≥ VOUT + 50 mV for full 1 A operation. |
| SNS | Output voltage sensing input | Connected directly to VOUT pad on PCB to enable accurate closed-loop regulation for fixed-output version. |
| GND | Ground reference | Common return path for VIN, VOUT, VBIAS, and EN; must be low-impedance and thermally coupled to PCB ground plane. |
| EN | Logic-level enable control | Active-high input (VEN(H) = 0.9 V); drives regulator ON/OFF; internal pull-down ensures default-off state if left floating. |
| VBIAS | Bias supply for internal circuitry | Powers control logic and reference independently; monitored by UVLO; minimum 3.0 V required for operation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dropout | 50 mV typical at 1 A - enables use with near-threshold input voltages, maximizing battery utilization in portable devices. |
| Separate VBIAS rail | 3.0–5.5 V bias supply - isolates control circuitry from noisy or drooping main input, improving PSRR and transient response. |
| Active output discharge | Integrated 150 Ω pull-down (NCP139A variant) - rapidly discharges VOUT when disabled, preventing floating states in multi-rail systems. |
| Stable with 10 µF ceramic | No ESR requirement - eliminates need for tantalum or aluminum electrolytic capacitors, reducing size, cost, and failure risk. |
| Low bias quiescent current | 35 µA typical - minimizes standby power draw in always-on subsystems like modem or sensor hubs. |
| Thermal protection | 160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload without external thermal monitoring. |
Applications
| Smartphone Application Processor Core Rail | Tablet Memory I/O Supply |
|---|---|
Use Scenario: Powering ARM Cortex-A series CPU cores requiring tightly regulated 1.8 V with fast transient response during burst-mode operation. IC Role / Device Role / Timing Role: Post-regulator for buck converter output, providing clean, low-noise 1.8 V with <50 mV dropout to maintain voltage during high-current CPU load steps. Use Value: Enables reliable core operation down to 1.85 V input, extending usable battery voltage range by ~120 mV versus standard LDOs. | Use Scenario: Supplying LPDDR4/LPDDR5 I/O banks in tablets where noise immunity and space constraints are critical. IC Role / Device Role / Timing Role: Low-noise, high-PSRR voltage source decoupling high-speed memory interface signals from switching noise on main PMIC rails. Use Value: 75 dB PSRR at 1 kHz suppresses DC/DC ripple, reducing bit error rates and enabling higher memory clock stability. |
| Wireless Camera Module Power | DVR Image Signal Processor (ISP) Rail |
Use Scenario: Delivering 1.8 V to CMOS image sensors and companion ASICs in compact wireless security cameras. IC Role / Device Role / Timing Role: Primary voltage regulator for noise-sensitive analog front-end circuits, leveraging ultra-low 35 µVRMS output noise. Use Value: Minimizes sensor readout noise floor, improving dynamic range and low-light SNR without adding shielding or filtering. | Use Scenario: Powering ISP digital logic blocks requiring precise 1.8 V with fast enable/disable control during video recording start/stop. IC Role / Device Role / Timing Role: Enable-controlled rail with active discharge, ensuring rapid power-down and safe reset sequencing between video sessions. Use Value: Integrated 150 Ω discharge path clears VOUT within microseconds, eliminating hold-up time and preventing latch-up in downstream logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI TPS7A2018PDQNR | Fixed 1.8 V, 300 mA max, no VBIAS rail, 125 mV dropout at 300 mA | Limited to lower-current peripherals; lacks dual-rail architecture for high-PSRR bias isolation | Select when total load ≤300 mA and board space allows larger SOT-23-5 package; not suitable for 1 A loads. |
| ROHM BD3985FVM-TR | Fixed 1.8 V, 1 A, single-rail (no VBIAS), 150 mV dropout at 1 A, 60 dB PSRR | Higher dropout and lower PSRR reduce battery efficiency and noise rejection in demanding RF/analog apps | Choose for cost-sensitive designs where 150 mV dropout and 60 dB PSRR meet requirements; requires larger 2.0×2.0 mm DFN package. |
Compared with TPS7A2018PDQNR and BD3985FVM-TR, the NCP139AFCT180T2G uniquely combines 1 A capability, 50 mV dropout, dual-rail bias isolation, and 85 dB VBIAS PSRR - making it the only option capable of maintaining 1.8 V regulation under tight input headroom while rejecting noise from both power and bias domains.
Availability
NCP139AFCT180T2G is available at Aetrix Electronics and suitable for smartphone processor core rails, tablet memory I/O supplies, wireless camera module power, and DVR ISP rails requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for NCP139AFCT180T2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP139AFCT180T2G belongs to onsemi's high-performance VLDO regulator product line, engineered specifically for noise-sensitive, space-constrained portable electronics requiring dual-rail operation and ultra-low dropout under 1 A loads.
FAQ
What is the output voltage of the NCP139AFCT180T2G?
The NCP139AFCT180T2G delivers a fixed 1.8 V output voltage with ±1.0% accuracy over −40°C to +85°C. This value is factory-trimmed and does not require external feedback components, simplifying design for dedicated 1.8 V rails in mobile processors and memory interfaces.
Does the NCP139AFCT180T2G require an external bias supply?
Yes, the NCP139AFCT180T2G requires a separate VBIAS supply between 3.0 V and 5.5 V to power its internal control circuitry. This bias rail is independent of VIN and enables superior PSRR (85 dB at 1 kHz) and stable operation even when VIN sags near VOUT.
What package type is used for the NCP139AFCT180T2G?
The NCP139AFCT180T2G uses the WLCSP6 package (1.2 mm × 0.8 mm, 0.4 mm pitch, Case 567MV), a wafer-level chip-scale package optimized for ultra-dense PCB layouts in smartphones and wearables, with RJA = 69°C/W under JEDEC-standard test conditions.
Does the NCP139AFCT180T2G include active output discharge?
Yes, the NCP139AFCT180T2G includes integrated active output discharge (a feature of the "A" variant), providing a 150 Ω pull-down path from VOUT to GND when EN is low - ensuring rapid discharge of output capacitance for safe power sequencing in multi-rail systems.
What is the minimum input voltage required for full 1 A operation of the NCP139AFCT180T2G?
For full 1 A output at 1.8 V, the NCP139AFCT180T2G requires VIN ≥ 1.85 V (VOUT + 50 mV typ. dropout). At lower VIN, current capability degrades per the dropout curve in Figure 3 of the datasheet; operation below 1.85 V is possible but limited to reduced load currents.
NCP139AFCT180T2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 1.5V @ 1A
- Current - Output:
- 1A
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 85dB ~ 70dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WLCSP (1.2x0.8)
NCP139AFCT180T2G FAQ
1.How can I place an order for NCP139AFCT180T2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP139AFCT180T2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP139AFCT180T2G reliable?
The price and inventory of NCP139AFCT180T2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP139AFCT180T2G is usually 5 days.
3.What payment methods are accepted for NCP139AFCT180T2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP139AFCT180T2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP139AFCT180T2G?
NCP139AFCT180T2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP139AFCT180T2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP139AFCT180T2G?
For technical support, including NCP139AFCT180T2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP139AFCT180T2G requirements.
6.How does Aetrix verify that NCP139AFCT180T2G is sourced from the original manufacturer or authorized distributors?
All NCP139AFCT180T2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP139AFCT180T2G meets industry standards.
7.What is the process for return or replacement of NCP139AFCT180T2G?
All NCP139AFCT180T2G units undergo pre-shipment inspection (PSI). If there is an issue with NCP139AFCT180T2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP139AFCT180T2G part is unused and in its original packaging.
Return procedure for NCP139AFCT180T2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP139AFCT180T2G Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

