onsemi NCP1509MNR2
- Part No.:
- NCP1509MNR2
- Manufacturer:
- onsemi
- Package:
- -
- Datasheet:
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NCP1509MNR2.pdf
- Description:
- IC REG LINEAR SWITCHING REG
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Product details
Overview
NCP1509MNR2 from onsemi is a synchronous step-down DC-DC converter optimized for portable battery-powered systems, delivering up to 500 mA output at 1.05–1.8 V with digital voltage selection, 1 MHz PWM or pulsed switching mode operation, and integrated soft-start, current limiting, and thermal shutdown. It targets space-constrained applications such as smartphones and digital cameras powered by single-cell Li-ion (2.7–5.2 V input).
For engineers reviewing the NCP1509MNR2 datasheet, pinout, applications, or equivalent options, key selection criteria include its 10-pin DFN package, programmable output voltages, light-load pulsed mode (14 µA quiescent current), 800 mA cycle-by-cycle current limit in PWM mode, and SYNC-controlled mode selection between internal oscillator (≈1 MHz), external synchronization (500–1000 kHz), or low-power pulsed operation.
Technical Context
The NCP1509MNR2 implements current-mode PWM control with integrated compensation, enabling stable regulation across input (2.7–5.2 V) and load (0–500 mA) variations. Its dual-mode architecture-PWM for heavy loads and pulsed switching for light loads (<30 mA)-is selected via the SYNC pin, which also accepts external clock signals for system-level timing alignment.
Output voltage is digitally set using CB0/CB1 logic states (1.05/1.35/1.57/1.8 V), with internal pull-up/pull-down resistors enabling default 1.35 V operation when floating. The device integrates synchronous P-FET/N-FET power switches (RDS(on) ≈ 0.23 Ω), eliminating external diodes and supporting high efficiency (up to 92.5% at 1.8 V/125 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.2 V - supports single-cell Li-ion and 3-cell alkaline/NiMH batteries without external regulators. |
| Output Voltage Options | 1.05 V, 1.35 V, 1.57 V, or 1.8 V - digitally selectable via CB0/CB1 pins; enables dynamic core voltage scaling in baseband processors. |
| Max Output Current | 500 mA at VIN = 3.6 V - sufficient for powering DSPs, RF transceivers, and memory subsystems in portable devices. |
| Quiescent Current | 14 µA in pulsed mode - minimizes battery drain during standby or low-activity periods in always-on subsystems. |
| Switching Frequency | 1 MHz nominal (internal oscillator); 500–1000 kHz (external sync) - enables use of compact 6.8 µH inductors and low-profile ceramic capacitors. |
| Current Limit | 800 mA (PWM mode), 200 mA (pulsed mode) - provides robust short-circuit and overload protection with cycle-by-cycle monitoring. |
| Operating Temperature | −30°C to +85°C ambient - validated for consumer handheld environments including cellular phones and digital cameras. |
Pinout & Package
Package: 3 mm × 3 mm, 10-pin DFN (Case 485C), exposed thermal pad, Pb-free (RoHS-compliant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 GNDA | Analog Ground | Reference ground for FB, SYNC, CB0, CB1, SHD - must be star-connected separately from power ground to avoid noise coupling. |
| 2 GNDP | Power Ground | Return path for high-current P-FET/N-FET switching stage - connects directly to exposed thermal pad for thermal and EMI performance. |
| 3 LX | Power Switch Node | Drain connection of internal P-FET and source of N-FET - drives external inductor; requires low-inductance layout to minimize ringing. |
| 4 VCCP | P-FET Supply Input | Bias supply for high-side switch - decoupled with local 10 µF ceramic capacitor placed near pin. |
| 5 VCCA | Analog Supply Input | Power for error amplifier, reference, and control logic - separate from VCCP to isolate analog noise from switching transients. |
| 6 FB | Voltage Feedback Input | Resistive divider input referenced to internal 0.8 V bandgap - accuracy ±3% over temperature ensures tight output regulation (±15 mV line/load regulation). |
| 7 CB0 | Digital Output Select | Logic input with internal pulldown - combined with CB1 determines output voltage per truth table (e.g., CB0=L, CB1=H → 1.35 V). |
| 8 CB1 | Digital Output Select | Logic input with internal pullup - floating state defaults to 1.35 V output; no external bias required. |
| 9 SHD | Enable/Shutdown Control | Active-high enable with internal pulldown - <0.4 V disables IC (0.1 µA shutdown current); >1.2 V initiates soft-start sequence. |
| 10 SYNC | Mode Control & Sync Input | Three-state pin: LOW = pulsed mode; HIGH = 1 MHz PWM; external 500–1000 kHz clock = synchronized PWM - enables system-level power coordination. |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous Rectification | Integrated P-FET/N-FET replaces external Schottky diode, reducing conduction loss and improving efficiency by ~5–10% vs. asynchronous designs. |
| Dual-Mode Operation | Automatic transition between high-efficiency PWM (≥100 mA) and ultra-low-IQ pulsed mode (<30 mA) - extends battery life without firmware intervention. |
| Digital Output Programming | Four factory-set output voltages selected by two logic inputs - eliminates external resistor networks and supports software-controlled DVFS in application processors. |
| Integrated Protection | Cycle-by-cycle current limiting (800 mA PWM / 200 mA PM), thermal shutdown (160°C trip), and overvoltage protection (5% above setpoint) - prevents damage under fault conditions without external components. |
| Fixed Internal Compensation | No external compensation network required - simplifies design, reduces BOM count, and guarantees stability with recommended 6.8 µH inductor and 22 µF ceramic output capacitor. |
Applications
| Smartphone Baseband Power | Digital Camera Image Sensor Bias |
|---|---|
Use Scenario: Powers ARM-based baseband processor cores requiring dynamically scaled supply voltages (1.05–1.8 V) during varying computational loads. IC Role / Device Role / Timing Role: Primary synchronous buck regulator with digital voltage selection and pulsed mode for sleep-state current reduction. Use Value: Enables >20% longer talk time via 14 µA quiescent current in pulsed mode and precise 1.35 V default output matching typical baseband Vcore requirements. | Use Scenario: Supplies regulated 1.57 V to CMOS image sensor analog front-end during preview and capture modes. IC Role / Device Role / Timing Role: Low-noise, fast-transient response DC-DC converter synchronized to camera frame timing via SYNC pin. Use Value: Achieves <5 mVpp output ripple and <50 mV load transient deviation, preserving image SNR and preventing pixel corruption during exposure bursts. |
| Wireless Modem RF Core Supply | Portable Audio Codec Power |
Use Scenario: Delivers clean 1.8 V power to LTE/Wi-Fi modem RF transceiver ICs operating across wide temperature ranges (−30°C to +85°C). IC Role / Device Role / Timing Role: High-efficiency step-down regulator with thermal shutdown and 5.2 V max input tolerance for USB-powered modems. Use Value: Maintains >90% efficiency at 300 mA load and survives 125°C junction temperature excursions, ensuring reliable data transmission in compact enclosures. | Use Scenario: Provides 1.05 V bias to low-power audio DAC/ADC in MP3 players and Bluetooth headsets. IC Role / Device Role / Timing Role: Ultra-low-quiescent-current buck converter operating in pulsed mode during audio playback pause or standby. Use Value: Reduces system standby current to <1 µA (including IC and LDO downstream), extending battery life beyond 100 hours in portable audio devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down DC-DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62231DRVR | 3 MHz fixed-frequency PWM; 300 mA max output; no pulsed mode; different pinout and feedback reference (0.6 V). | Better suited for space-constrained, high-frequency designs where light-load efficiency is secondary to size. | Select TPS62231DRVR only if board layout prioritizes 2×2 mm QFN footprint and system clock synchronization is unnecessary. |
| RT8059ZSP | 2.5 MHz operation; 600 mA output; built-in enable but no SYNC pin for mode selection or external clock sync. | Targeted at cost-sensitive consumer electronics where digital voltage selection and multi-mode operation are not required. | Choose RT8059ZSP when fixed 1.2 V or 1.8 V output suffices and PCB area is less constrained than in smartphone modules. |
Compared with TPS62231DRVR and RT8059ZSP, the NCP1509MNR2 uniquely combines digital output programming, dual-mode efficiency optimization (14 µA pulsed IQ), and SYNC-based system-level timing control - making it the preferred choice for battery-life-critical portable devices requiring flexible voltage scaling and adaptive power management.
Availability
NCP1509MNR2 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, wireless modem RF core supply, portable audio codec power, and industrial handheld metering requiring stable component supply across extended temperature and long production lifecycles.
Supply support for NCP1509MNR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, delivering silicon solutions for automotive, industrial, cloud, and portable markets.
The NCP1509MNR2 belongs to onsemi's high-efficiency DC-DC converter product line, engineered specifically for portable battery-powered equipment where small footprint, multi-voltage flexibility, and adaptive light-load operation are critical design requirements.
FAQ
What output voltages does the NCP1509MNR2 support, and how are they selected?
The NCP1509MNR2 supports four fixed output voltages: 1.05 V, 1.35 V, 1.57 V, and 1.8 V. Selection is achieved using the logic states of CB0 (pin 7) and CB1 (pin 8), with internal pull-down (CB0) and pull-up (CB1) resistors enabling default 1.35 V operation when both pins float. The truth table is documented in the datasheet: CB0=L/CB1=L → 1.05 V; CB0=L/CB1=H → 1.35 V; CB0=H/CB1=H → 1.57 V; CB0=H/CB1=L → 1.8 V. This digital configuration eliminates external resistor dividers and supports software-controlled DVFS in host processors.
How does the NCP1509MNR2 manage efficiency across varying load conditions?
The NCP1509MNR2 uses dual-mode operation to maintain high efficiency across load ranges: PWM mode (up to 500 mA) with ≈1 MHz switching delivers >91% efficiency at 300 mA, while pulsed mode (<30 mA) reduces quiescent current to 14 µA - extending battery life during standby. Mode selection is controlled by the SYNC pin: LOW enables pulsed mode; HIGH or external clock (500–1000 kHz) activates PWM. This adaptive behavior is fully integrated, requiring no external circuitry or firmware control, and is validated across −30°C to +85°C.
What protection features are integrated into the NCP1509MNR2?
The NCP1509MNR2 integrates five key protections: (1) cycle-by-cycle current limiting (800 mA in PWM, 200 mA in pulsed mode), (2) thermal shutdown (160°C trip, 135°C restart hysteresis), (3) output overvoltage protection (5% above nominal setpoint), (4) soft-start (≈1.5 ms ramp to limit inrush), and (5) shutdown mode with 0.1 µA typical current draw. All functions operate autonomously using internal references and comparators - no external components are needed for basic fault coverage, simplifying design and improving reliability in portable systems.
Can the NCP1509MNR2 be synchronized to an external clock, and what are the requirements?
Yes, the NCP1509MNR2 can be synchronized to an external clock applied to the SYNC pin (pin 10). The acceptable frequency range is 500 kHz to 1000 kHz, with input voltage thresholds of 400–830 mV (LOW) and 920–1200 mV (HIGH). The device triggers switching on the rising edge of the external clock signal. Synchronization allows system-level timing coordination - for example, aligning switching noise away from sensitive RF bands or matching frame timing in imaging systems - and maintains full PWM functionality including current-mode control and output regulation.
What is the recommended inductor and capacitor configuration for the NCP1509MNR2?
The NCP1509MNR2 is optimized for a 6.8 µH shielded power inductor (e.g., TDK VLCF4020-6R8) and ceramic capacitors: 10 µF input (X5R, 6.3 V) placed near VCCA/VCCP pins, and 22 µF output (X5R, 6.3 V) with low ESR (<20 mΩ) such as TDK C2012X5R0J226. These values are validated for ≤10 mV ripple at 300 mA and ensure stability with the device's fixed internal compensation. Layout best practices include star-grounding GNDA/GNDP at the exposed pad, minimizing high-current loop area (LX–inductor–Cout–GNDP), and routing FB away from noisy traces.
NCP1509MNR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- -
- Output Configuration:
- -
- Topology:
- -
- Output Type:
- -
- Number of Outputs:
- -
- Voltage - Input (Min):
- -
- Voltage - Input (Max):
- -
- Voltage - Output (Min/Fixed):
- -
- Voltage - Output (Max):
- -
- Current - Output:
- -
- Frequency - Switching:
- -
- Synchronous Rectifier:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
NCP1509MNR2 FAQ
1.How can I place an order for NCP1509MNR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP1509MNR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP1509MNR2 reliable?
The price and inventory of NCP1509MNR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP1509MNR2 is usually 5 days.
3.What payment methods are accepted for NCP1509MNR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP1509MNR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP1509MNR2?
NCP1509MNR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP1509MNR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP1509MNR2?
For technical support, including NCP1509MNR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP1509MNR2 requirements.
6.How does Aetrix verify that NCP1509MNR2 is sourced from the original manufacturer or authorized distributors?
All NCP1509MNR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP1509MNR2 meets industry standards.
7.What is the process for return or replacement of NCP1509MNR2?
All NCP1509MNR2 units undergo pre-shipment inspection (PSI). If there is an issue with NCP1509MNR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP1509MNR2 part is unused and in its original packaging.
Return procedure for NCP1509MNR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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