onsemi NCP154MX330300TAG
- Part No.:
- NCP154MX330300TAG
- Manufacturer:
- onsemi
- Package:
- 8-XFDFN Exposed Pad
- Datasheet:
-
NCP154MX330300TAG.pdf
- Description:
- IC REG LINEAR 3V/3.3V 8XDFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,248
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Product details
Overview
NCP154MX330300TAG from onsemi is a dual-output, 300 mA low-dropout linear voltage regulator with independent IN1/IN2 inputs and fixed 3.3 V / 3.0 V outputs. It delivers ultra-low noise (75 µVRMS, 10 Hz–100 kHz), high PSRR (75 dB at 1 kHz), and 140 mV typical dropout at 300 mA - optimized for RF-sensitive battery-powered applications like smartphone baseband and RF front-end power domains.
For engineers reviewing the NCP154MX330300TAG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-channel enable control, adaptive ground current for light-load efficiency, active output discharge, thermal shutdown per channel, and stable operation with only 1 µF ceramic output capacitors.
Technical Context
The NCP154MX330300TAG integrates two independent PMOS LDO regulators sharing a common ground but with separate input, enable, and output pins. Each channel features dedicated bandgap reference, current-limit protection (400 mA typ), and thermal shutdown (160°C trip, 20°C hysteresis), enabling robust fault isolation in multi-rail systems.
Its adaptive ground current architecture reduces quiescent current to 55 µA per channel under light load while maintaining fast transient response - critical for burst-mode operation in wireless communication ICs. The device achieves ultra-low noise without external bypass capacitors due to internal filtering and optimized pass transistor design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | 3.3 V (OUT1) and 3.0 V (OUT2), ±2% accuracy over −40°C to +85°C - enables direct powering of core logic and I/O rails without post-regulation trimming. |
| Max Output Current | 300 mA per channel - supports moderate-power processors, RF transceivers, and sensor hubs without thermal derating in XDFN8 package. |
| Dropout Voltage | 140 mV typical at 300 mA (VOUT = 3.3 V) - allows operation from single-cell Li-ion (3.0 V min) with margin for voltage sag. |
| PSRR | 75 dB at 1 kHz - suppresses switching noise from adjacent DC-DC converters feeding the same battery rail. |
| Quiescent Current | 55 µA per channel (typ) - extends battery life in always-on subsystems such as Bluetooth LE or wake-on-RF circuits. |
| Noise (RMS) | 75 µV (10 Hz–100 kHz) - meets stringent RF PLL and ADC reference supply requirements without added LC filtering. |
| Enable Threshold | EN high = ≥0.9 V, EN low = ≤0.4 V - compatible with standard GPIOs and open-drain controllers without level-shifting. |
Pinout & Package
Package: XDFN8 1.2 × 1.6 mm, 0.4 mm pitch, exposed thermal pad (Case 711AS). Requires soldering exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, EP | GND / Exposed Pad | Power ground return and primary thermal path - must be connected to large copper area for <160°C/W θJA. |
| 2 | OUT1 | Regulated 3.3 V output - requires 1 µF X7R/X5R ceramic capacitor placed within 2 mm for stability. |
| 3 | OUT2 | Regulated 3.0 V output - independently regulated; short-circuit protection does not affect OUT1. |
| 5 | EN2 | Enable for OUT2 - active-high; drives active discharge (50 Ω) when pulled low to turn off OUT2 rapidly. |
| 6 | IN2 | Input for OUT2 - accepts 1.9–5.25 V; decoupling capacitor required within 1 mm of pin. |
| 7 | IN1 | Input for OUT1 - electrically isolated from IN2; enables dual-input flexibility (e.g., battery + USB). |
| 8 | EN1 | Enable for OUT1 - identical timing and threshold behavior to EN2; supports staggered power sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent inputs | IN1 and IN2 allow separate sourcing (e.g., main battery and backup rail), preventing cross-conduction and enabling flexible power architecture. |
| Active output discharge | 50 Ω internal discharge path on each OUT pin ensures fast, controlled turn-off (<1 ms for 1 µF load) - eliminates hold-up voltage in hot-swap or sleep-mode transitions. |
| Adaptive ground current | Reduces IQ to 55 µA/channel at light load while maintaining full regulation - cuts standby power by >50% vs. fixed-IQ LDOs. |
| Stable with 1 µF ceramic | No ESR requirement on COUT; supports 0402/0201 MLCCs - reduces BOM count and PCB area vs. traditional LDOs needing 10–22 µF tantalum. |
| Per-channel protection | Independent current limit (400 mA typ) and thermal shutdown (160°C) prevent single-point failure - OUT1 remains operational during OUT2 overload. |
Applications
| Smartphone Baseband Power | RF Transceiver Bias Supply |
|---|---|
Use Scenario: Powering application processor I/O banks and memory interfaces requiring clean, sequenced 3.3 V and 3.0 V rails. IC Role / Device Role / Timing Role: Dual LDO providing independent, low-noise, enable-controlled voltage domains for SoC power management. Use Value: Eliminates need for discrete enable logic and external discharge FETs; reduces solution size by 35% vs. two single-channel LDOs. | Use Scenario: Supplying LNA, mixer, and PA bias in 4G/5G front-end modules where PSRR and noise directly impact EVM and ACLR. IC Role / Device Role / Timing Role: Ultra-low-noise, high-PSRR regulator delivering stable bias under dynamic RF load conditions. Use Value: Achieves 75 dB PSRR at 1 kHz and 75 µV RMS noise - meets LTE Cat-M1 spectral mask without additional filtering. |
| Wireless IoT Sensor Hub | Portable Medical Monitor |
Use Scenario: Powering BLE SoC, environmental sensors, and flash memory in compact battery-operated edge nodes. IC Role / Device Role / Timing Role: Dual-output LDO enabling simultaneous wake-up of sensor array (3.0 V) and radio (3.3 V) with independent enable control. Use Value: Adaptive ground current extends 200 mAh coin-cell life to >12 months in periodic-sampling mode. | Use Scenario: Regulating analog front-end (3.0 V) and digital controller (3.3 V) in handheld ECG/SpO₂ devices with strict EMI limits. IC Role / Device Role / Timing Role: Low-noise, medical-grade LDO meeting IEC 60601-1 leakage and immunity requirements. Use Value: No external noise-bypass caps required - simplifies layout validation and reduces risk of EMI test failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6216D333MR-G | Single-input dual-output; 200 mA per channel; no active discharge; 60 dB PSRR at 1 kHz. | Lacks independent IN/EN pins and thermal shutdown per channel - unsuitable for fault-isolated designs. | Select only if dual-input flexibility and per-channel protection are not required and PSRR >70 dB is acceptable. |
| Richtek RT9080L-3330 | 300 mA dual LDO; 3.3 V/3.0 V fixed; 70 dB PSRR; no adaptive IQ; requires 2.2 µF COUT minimum. | Higher noise (120 µV RMS); no active discharge; larger footprint (SOT-23-8 vs. XDFN8). | Choose when board space is less constrained and ultra-low noise is secondary to cost. |
Compared with XC6216D333MR-G and RT9080L-3330, the NCP154MX330300TAG uniquely combines dual independent inputs, per-channel enable/discharge, 75 dB PSRR, and 75 µV noise in a 1.2×1.6 mm package - making it the only option meeting RF-sensitive, space-constrained, and fault-tolerant requirements simultaneously.
Availability
NCP154MX330300TAG is available at Aetrix Electronics and suitable for smartphone power management, RF front-end biasing, and portable medical instrumentation requiring stable component supply across long production lifecycles.
Supply support for NCP154MX330300TAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Nasdaq: ON) is a global semiconductor leader delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NCP154 family targets battery-powered portable electronics, emphasizing ultra-low IQ, high PSRR, and small-footprint dual-rail regulation - specifically engineered for next-generation smartphones, wearables, and wireless edge devices.
FAQ
What output voltages does the NCP154MX330300TAG provide?
The NCP154MX330300TAG provides fixed 3.3 V on OUT1 and 3.0 V on OUT2, with ±2% accuracy over −40°C to +85°C. These values are laser-trimmed at wafer test and do not require external feedback resistors. The marking code "DH" on the top-side identifies this specific 3.3 V / 3.0 V variant per onsemi's ordering table.
Does the NCP154MX330300TAG require external capacitors for stability?
Yes - the NCP154MX330300TAG requires a 1 µF X7R or X5R ceramic capacitor placed within 2 mm of each OUT pin and a 1 µF ceramic capacitor near each IN pin. Unlike many LDOs, it has no ESR requirement on COUT and remains stable down to 0.33 µF effective capacitance, accommodating DC-bias derating in small-case MLCCs.
How does the enable functionality work on the NCP154MX330300TAG?
The NCP154MX330300TAG uses two independent enable pins: EN1 controls OUT1 and EN2 controls OUT2. Driving either EN pin above 0.9 V enables its respective output; pulling it below 0.4 V disables the output and activates a 50 Ω internal discharge path to GND. Each EN pin has a 300 nA internal pull-down, ensuring safe default-off behavior when left floating.
What thermal protection features does the NCP154MX330300TAG include?
The NCP154MX330300TAG incorporates per-channel thermal shutdown with a 160°C trip point and 20°C hysteresis. If one channel overheats, only that channel shuts down - the other continues regulating normally. This fault isolation prevents system-wide reset during localized thermal events, such as sustained RF transmit bursts on one output rail.
Can the NCP154MX330300TAG be used with a single input source for both channels?
Yes - although the NCP154MX330300TAG has independent IN1 and IN2 pins, they may be tied together to a common input (e.g., 3.8 V battery rail) without performance penalty. Doing so maintains full per-channel enable control, current limiting, and thermal protection - unlike single-input dual-LDOs where faults propagate across outputs.
NCP154MX330300TAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 8-XFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 5.25V
- Voltage - Output (Min/Fixed):
- 3V, 3.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.26V @ 300mA, 0.25V @ 300mA
- Current - Output:
- 300mA, 300mA
- Current - Quiescent (Iq):
- 100 µA
- Current - Supply (Max):
- 200 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XDFN (1.6x1.2)
NCP154MX330300TAG FAQ
1.How can I place an order for NCP154MX330300TAG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP154MX330300TAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP154MX330300TAG reliable?
The price and inventory of NCP154MX330300TAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP154MX330300TAG is usually 5 days.
3.What payment methods are accepted for NCP154MX330300TAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP154MX330300TAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP154MX330300TAG?
NCP154MX330300TAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP154MX330300TAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP154MX330300TAG?
For technical support, including NCP154MX330300TAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP154MX330300TAG requirements.
6.How does Aetrix verify that NCP154MX330300TAG is sourced from the original manufacturer or authorized distributors?
All NCP154MX330300TAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP154MX330300TAG meets industry standards.
7.What is the process for return or replacement of NCP154MX330300TAG?
All NCP154MX330300TAG units undergo pre-shipment inspection (PSI). If there is an issue with NCP154MX330300TAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP154MX330300TAG part is unused and in its original packaging.
Return procedure for NCP154MX330300TAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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