My Inquiry
My Account
onsemi NCP1578MNR2G
- Part No.:
- NCP1578MNR2G
- Manufacturer:
- onsemi
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
NCP1578MNR2G.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 20QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,338
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP1578MNR2G from onsemi is a synchronous step-down PWM controller with integrated 5 V/50 mA linear regulator, designed for battery-powered systems operating from 4.5 V to 24 V input. It delivers adjustable output voltage (via FB pin), features 1.5% reference accuracy at 0.8 V, programmable power-good delay, and lossless high-side RDS(ON) current sensing - enabling efficient microprocessor and DSP core supply in portable networking equipment.
For engineers reviewing the NCP1578MNR2G datasheet, pinout, applications, or equivalent options, key selection considerations include its QFN20 package, forced-PWM/power-saving mode control via FPWM pin, thermal shutdown at 150 °C, overvoltage protection at 115% of VFB, and compatibility with external N-channel high- and low-side MOSFETs.
Technical Context
The NCP1578MNR2G implements voltage-mode PWM control with input-voltage feedforward ramp generation, ensuring stable regulation across wide input ranges (4.5–24 V). Its error amplifier (70 dB DC gain, 2 MHz unity-gain bandwidth) drives an internal comparator against a fixed-frequency ramp derived from a 300 kHz oscillator.
Control logic integrates independent enable inputs (EN_SW for SMPS, EN_LDO for LDO5), adaptive non-overlap timing for TG/BG gate drivers, and cycle-by-cycle overcurrent protection triggered after 16 consecutive fault cycles. The device supports CCM, DCM, and pulse-skipping modes, with soft-start current fixed at 4.0 µA and PGOOD delay current at 2.0 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 24 V - supports 3–4 cell Li-ion batteries and universal AC/DC adapters without external pre-regulation. |
| SMPS Output Accuracy | ±1.5% at 0.8 V reference - ensures tight regulation for sensitive core voltages (e.g., 3.3 V, 2.5 V, 1.8 V) via resistor divider feedback. |
| Switching Frequency | 300 kHz ±10% - balances efficiency, EMI, and inductor size; fixed frequency enables predictable filter design. |
| LDO5 Output | 5.0 V ±3% @ 0–50 mA - powers internal circuitry and auxiliary rails; enabled/disabled independently via EN_LDO pin. |
| Overvoltage Threshold | 115% of VFB (typ) - latches off SMPS upon sustained overvoltage, protecting downstream loads like FPGAs or memory. |
| Thermal Shutdown | 150 °C trip, 125 °C hysteresis - prevents permanent damage during overload or poor heatsinking; QFN20 package has RθJA = 47 °C/W. |
| Soft-Start Current | 4.0 µA (typ) - sets controlled VOUT ramp rate via external capacitor; prevents inrush current and output overshoot. |
Pinout & Package
Package: QFN20 (MN suffix), 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad (THPAD) requiring connection to PCB ground plane for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FPWM | Mode control input | Logic-high forces continuous PWM; logic-low enables power-saving (DCM/pulse-skipping) for light-load efficiency. |
| EN_LDO | LDO enable input | High enables 5 V/50 mA linear regulator; tolerates up to 27 V; UVLO threshold 4.1 V with 330 mV hysteresis. |
| OCSET | Current-sense threshold | Sets high-side MOSFET overcurrent limit via external resistor; hosts 40 µA current sink for lossless RDS(ON) sensing. |
| EN_SW | SMPS enable input | High enables PWM controller; thresholds at 1.4 V (ON) / 0.6 V (OFF); disables PGOOD when asserted low. |
| LDO5 | LDO output | Stable 5 V supply for internal logic and external bias; requires ≥1 µF ceramic bypass capacitor. |
| FB | Feedback input | Connects to resistor divider from SMPS output; regulates VOUT to 0.8 V reference with ±1.5% accuracy. |
| PGOOD | Open-drain status output | High-impedance when VOUT is within ±15% of target; pulled low on fault (OVP/UVP/OTP/UVLO) or EN_SW deassertion. |
| TG / BG | Gate drivers | TG drives high-side N-FET gate referenced to SWN; BG drives low-side N-FET gate referenced to PGND; both feature 1.5–4.0 Ω drive strength. |
| VBST | Bootstrap supply | Connects boost capacitor between VBST and SWN to generate >5 V gate drive for high-side FET. |
| SWN | Switch node | Inductor connection point; return path for high-side gate driver; withstands −0.3 V (DC) to +32 V transient. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 5 V/50 mA LDO | Eliminates need for external bias rail; powers internal circuitry and can supply auxiliary loads such as level shifters or sensors. |
| Programmable PGOOD delay | External capacitor on PGDLY pin sets delay time before PGOOD asserts, allowing output stabilization before system release. |
| Lossless high-side current sensing | Uses OCSET pin's 40 µA sink and MOSFET RDS(ON) to detect overcurrent without sense resistor losses or board area. |
| Adaptive non-overlap timing | Prevents shoot-through current between TG and BG outputs by dynamically adjusting dead time, improving efficiency and reliability. |
| Independent enable controls | EN_LDO and EN_SW allow staged power-up sequencing - e.g., enable LDO5 first, then SMPS after internal logic stabilizes. |
Applications
| Network Router Power Supply | Li-ion Powered Embedded Controller |
|---|---|
|
Use Scenario: Dual-rail power delivery in compact SOHO routers requiring 3.3 V for PHY/MAC and 5 V for USB ports. IC Role / Device Role / Timing Role: NCP1578MNR2G acts as primary SMPS controller with integrated LDO5 supplying 5 V bus while regulating 3.3 V via FB divider. Use Value: Single-chip solution reduces BOM count and layout area; forced-PWM mode ensures low-noise 3.3 V for Ethernet PHY timing integrity. |
Use Scenario: Core voltage regulation for ARM-based industrial controllers powered by 3-cell Li-ion (9–12.6 V). IC Role / Device Role / Timing Role: NCP1578MNR2G provides tightly regulated 1.2 V core supply (via FB divider) and powers controller peripherals from LDO5. Use Value: Power-saving mode extends battery runtime during idle; thermal shutdown protects against enclosure overheating in sealed enclosures. |
| Microprocessor Core Supply | LCD Display Backlight Driver Bias |
|
Use Scenario: High-accuracy, low-noise 1.8 V supply for FPGA or DSP core in portable test equipment. IC Role / Device Role / Timing Role: NCP1578MNR2G serves as main buck controller; its 0.8 V reference and 1.5% accuracy enable precise 1.8 V via 1.25× divider ratio. Use Value: Soft-start prevents core voltage overshoot during cold boot; PGOOD signals FPGA configuration readiness to host MCU. |
Use Scenario: Stable 5 V bias rail for LED driver ICs and display timing controllers in handheld medical displays. IC Role / Device Role / Timing Role: NCP1578MNR2G's LDO5 output supplies 5 V to display interface logic while SMPS generates 3.3 V for backlight PWM IC. Use Value: Independent EN_LDO control allows display subsystem to remain active during main processor sleep; low dropout ensures regulation down to 4.5 V battery. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2451DT-LF-Z | Fixed 300 kHz frequency, no integrated LDO, requires external bias; smaller 8-pin SOIC package. | Lacks 5 V LDO and independent EN_LDO/EN_SW controls; suitable only where external 5 V rail exists. | Select MP2451DT-LF-Z if board space is constrained and 5 V is already available; avoid when LDO integration simplifies power architecture. |
| TPS54202HDDCR | Includes integrated 5 V LDO (100 mA), higher 2 A integrated FETs, but no OCSET-based lossless sensing. | Monolithic design eliminates external MOSFETs but limits max current and thermal headroom vs. NCP1578MNR2G's discrete FET flexibility. | Choose TPS54202HDDCR for lower component count in <2 A applications; retain NCP1578MNR2G for >3 A designs or where discrete FET optimization is critical. |
Compared with MP2451DT-LF-Z and TPS54202HDDCR, the NCP1578MNR2G uniquely combines external FET scalability, lossless current sensing, and dual independent enable controls - making it optimal for high-reliability, thermally demanding, or multi-rail battery-powered systems where LDO integration and fault granularity matter.
Availability
NCP1578MNR2G is available at Aetrix Electronics and suitable for network infrastructure, portable medical devices, and industrial embedded controllers requiring stable component supply, long-term lifecycle support, and Pb-free compliance.
Supply support for NCP1578MNR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, and sensor solutions for automotive, industrial, and cloud infrastructure markets.
The NCP1578MNR2G belongs to onsemi's high-efficiency DC-DC controller product line, engineered specifically for battery-operated systems needing flexible, reliable, and thermally robust power conversion with integrated bias capability.
FAQ
What is the maximum input voltage rating for the NCP1578MNR2G?
The NCP1578MNR2G supports a maximum VBAT of 27 V under absolute ratings, with recommended operation up to 24 V. Exceeding 24 V may trigger undervoltage lockout or reduce reliability; the device is optimized for 4.5–24 V battery/adaptor inputs, including 3–4 cell Li-ion packs.
Does the NCP1578MNR2G require external compensation components?
Yes, the NCP1578MNR2G requires external compensation on the COMP pin using a Type III network (R1, R3, R4, C1, C2, C3) to stabilize the voltage-mode control loop. This is necessary due to its open-loop error amplifier architecture and LC output filter; typical design targets 50% of switching frequency (≤150 kHz) for closed-loop bandwidth.
How does the NCP1578MNR2G implement overcurrent protection?
The NCP1578MNR2G uses lossless high-side RDS(ON) sensing via the OCSET pin: a 40 µA current sink develops a voltage across the high-side FET's on-resistance, compared against SWN during blanking time. After 16 consecutive fault cycles, SMPS latches off - resetting only upon cycling EN_SW or LDO5.
Can the NCP1578MNR2G operate without the integrated LDO5 enabled?
Yes - the NCP1578MNR2G can operate with EN_LDO held low, disabling the internal 5 V LDO. In this configuration, VCCP must be supplied externally (e.g., from a separate 5 V rail), and internal logic remains functional as long as VCCP meets specifications. However, LDO5 is required to power the internal reference and error amplifier in single-supply mode.
What thermal management is required for the NCP1578MNR2G in continuous 3 A operation?
At 3 A output, the NCP1578MNR2G's QFN20 package requires a minimum 200 mm² copper pour connected to the THPAD thermal pad for effective heat dissipation. With RθJA = 47 °C/W, junction temperature rise exceeds safe limits above ~1.5 W dissipation without adequate copper; use internal layers and thermal vias to enhance conduction to inner ground planes.
NCP1578MNR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 300kHz
- Voltage/Current - Output 1:
- Controller
- Voltage/Current - Output 2:
- 5V, 50mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 4.5V ~ 24V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (4x4)
NCP1578MNR2G FAQ
1.How can I place an order for NCP1578MNR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP1578MNR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP1578MNR2G reliable?
The price and inventory of NCP1578MNR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP1578MNR2G is usually 5 days.
3.What payment methods are accepted for NCP1578MNR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP1578MNR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP1578MNR2G?
NCP1578MNR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP1578MNR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP1578MNR2G?
For technical support, including NCP1578MNR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP1578MNR2G requirements.
6.How does Aetrix verify that NCP1578MNR2G is sourced from the original manufacturer or authorized distributors?
All NCP1578MNR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP1578MNR2G meets industry standards.
7.What is the process for return or replacement of NCP1578MNR2G?
All NCP1578MNR2G units undergo pre-shipment inspection (PSI). If there is an issue with NCP1578MNR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP1578MNR2G part is unused and in its original packaging.
Return procedure for NCP1578MNR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP1578MNR2G Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
