onsemi NCP3121MNTXG
- Part No.:
- NCP3121MNTXG
- Manufacturer:
- onsemi
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
NCP3121MNTXG.pdf
- Description:
- IC REG BUCK ADJ 3A DL 32QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,121
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Product details
Overview
NCP3121MNTXG from onsemi is a dual-channel, non-synchronous PWM step-down DC/DC switching regulator delivering up to 3.0 A per channel with adjustable 200–750 kHz switching frequency, 0.8 V ±1.5% feedback reference, and out-of-phase operation for reduced input ripple. It integrates cycle-by-cycle current limiting, undervoltage lockout (UVLO), thermal shutdown, hiccup-mode overload protection, and auto-tracking/sequencing-designed for powering DSP/FPGA cores and multi-rail embedded systems.
For engineers reviewing the NCP3121MNTXG datasheet, pinout, applications, or equivalent options, key selection considerations include dual 3.0 A output capability, 4.5–13.2 V input range, QFN32 package thermal performance, soft-start programmability via external capacitor, and independent enable/PG/SEQ/SS pins for power sequencing in multi-voltage domain designs.
Technical Context
The NCP3121MNTXG uses a fixed-frequency voltage-mode PWM architecture with a shared master oscillator driving two identical channels in 180° phase opposition-reducing input capacitor RMS current and EMI. Each channel features an integrated high-side P-FET (RDS(on) = 250 mΩ typ at 25°C), transconductance error amplifier (1.0 mS typ), and dedicated COMP/FB/SS/PG pins.
It implements auto-tracking via dedicated TRACK1/2 pins, supports external soft-start timing (10 ms typical with 0.1 µF), and provides independent enable (EN1/EN2) and sequence (SEQ1/SEQ2) control for coordinated power-up/down of multiple rails-critical for FPGA core/I/O voltage sequencing and DSP supply ramp alignment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 13.2 V - supports 5 V, 12 V, and intermediate industrial bus rails without pre-regulation. |
| Output Current per Channel | 3.0 A continuous - sufficient for mid-power FPGA core (e.g., Xilinx Artix-7) or dual-core DSP applications. |
| Switching Frequency | 200–750 kHz (externally set via RT resistor) - enables trade-off between efficiency (lower fSW) and solution size (higher fSW). |
| Feedback Reference Voltage | 0.8 V ±1.5% - enables precise low-voltage outputs (e.g., 1.0 V, 1.2 V, 1.8 V) using standard resistor dividers. |
| High-Side RDS(on) | 250 mΩ (typ @ 25°C) - limits conduction loss at 3 A, supporting >85% efficiency at 12 VIN/5 VOUT. |
| Shutdown Supply Current | <100 µA - ensures ultra-low quiescent power during system sleep or standby modes. |
| UVLO Threshold | 4.3 V (rising), 4.1 V (falling) with 0.2 V hysteresis - prevents erratic startup under brown-out conditions. |
Pinout & Package
The NCP3121MNTXG is housed in a thermally enhanced 32-pin QFN package (Case 488AM), 5 mm × 5 mm × 0.85 mm, with exposed thermal pad (GND) for PCB heat dissipation. Pin pitch is 0.5 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1, SW2 (Pins 1, 31, 32 & 8–10) | Channel 1/2 switch node | Connects directly to inductor high-side; requires low-inductance layout to minimize switching noise and voltage spikes. |
| VIN (Pins 2–7), AVIN (Pin 25) | Main and analog input supply | VIN powers high-side FETs and logic; AVIN supplies internal reference/oscillator-both require local ceramic decoupling. |
| GND1, GND2, AGND, Exposed Pad | Power/analog ground nodes | Must be connected to a common low-impedance ground plane; exposed pad is primary thermal path and electrical GND. |
| FB1, FB2 (Pins 26, 15) | Output voltage feedback inputs | Accept resistive divider ratio to set output; 0.8 V reference enables accurate low-VOUT regulation. |
| EN1, EN2 (Pins 22, 20) | Independent channel enable inputs | Logic-high (>2.0 V) enables respective channel; pull-up current 4.0 µA allows direct MCU GPIO control. |
| PG1, PG2 (Pins 24, 23) | Open-drain power-good outputs | Assert high when output reaches ≥90% of target; requires external pull-up for system monitoring or sequencing logic. |
| RT (Pin 16) | Oscillator frequency programming | Resistor to AGND sets fSW; open = 200 kHz default; 52.3 kΩ = ~635 kHz (typ). |
| TRACK1/2 (Pins 18, 17), SEQ1/2 (Pins 21, 19) | Tracking & sequencing control | Enable synchronized ramp-up/down of multiple rails; TRACK pins accept external voltage for custom slew rate control. |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase dual-channel operation | 180° phase shift reduces input ripple current by ~30%, allowing smaller input bulk capacitors and lower EMI filter cost. |
| Auto-tracking and sequencing | TRACK/SEQ pins support hardware-controlled voltage ramp alignment-essential for FPGA core/I/O rail sequencing without external controllers. |
| Programmable soft-start | External SS1/SS2 capacitor sets startup time (e.g., 0.1 µF → 10 ms); prevents inrush current stress on input supply and output caps. |
| Hiccup-mode overload protection | Discharges SS capacitor to 0.1 V on fault, then re-attempts start-up-prevents thermal runaway during sustained short-circuit conditions. |
| Stable with low-ESR ceramic output caps | No need for electrolytic or tantalum; enables compact, high-reliability designs with fast transient response and no lifetime derating. |
Applications
| Application 1 | Application 2 |
|---|---|
Use Scenario: Powering Xilinx Artix-7 FPGA core (VCCINT) and auxiliary I/O bank (VCCO) from a single 12 V rail. IC Role / Device Role / Timing Role: Dual-channel buck regulator providing independently regulated 1.0 V (core) and 3.3 V (I/O) with synchronized startup via TRACK/SEQ pins. Use Value: Eliminates need for discrete sequencing IC or FPGA-configurable power management; meets Xilinx's 100 ms max ramp time and monotonic rise requirements. | Use Scenario: Supplying dual-core TMS320C6748 DSP requiring separate 1.2 V core and 3.3 V I/O voltages with controlled power-up order. IC Role / Device Role / Timing Role: Dual buck controller implementing core-first sequencing using EN1/EN2 and SEQ1/SEQ2 pins to meet TI's boot voltage ordering spec. Use Value: Guarantees core voltage stabilizes before I/O, preventing latch-up or undefined state during reset assertion. |
| Application 3 | Application 4 |
Use Scenario: Generating 1.8 V and 2.5 V rails for high-speed ADC/DAC signal chain in medical imaging front-end. IC Role / Device Role / Timing Role: Low-noise dual regulator with out-of-phase switching minimizing shared input impedance coupling between analog and digital supplies. Use Value: Reduces PSRR-sensitive supply crosstalk; achieves <−60 dB PSRR at 100 kHz without additional ferrite beads or LC filters. | Use Scenario: Powering dual-rail SoC in set-top box with thermal constraints limiting board area for heatsinking. IC Role / Device Role / Timing Role: Thermally optimized QFN32 regulator with exposed pad tied to internal ground plane, enabling 3 A/channel operation at 65°C ambient. Use Value: Delivers full rated current without external MOSFETs or heatsinks-reducing BOM count and assembly cost vs. discrete solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2491DS-LF-Z | Single-channel 3 A buck; no tracking/sequencing; 0.8 V ref; 4.5–18 V input; 500 kHz fixed fSW | Requires two ICs for dual-rail; lacks hardware sequencing; simpler layout but higher component count. | Choose when cost-per-rail is prioritized over integration and sequencing control. |
| TPS54332DDAR | Single-channel 3.5 A buck; 0.8 V ref; 3.5–28 V input; 600 kHz fixed fSW; no TRACK/SEQ pins | Higher input voltage range; no native dual-channel coordination; needs external logic for sequencing. | Prefer when input exceeds 13.2 V or higher peak current margin is required per rail. |
Compared with MP2491DS-LF-Z and TPS54332DDAR, the NCP3121MNTXG uniquely integrates dual 3 A channels with hardware-based tracking, sequencing, and out-of-phase operation-reducing total solution size, eliminating external coordination circuitry, and simplifying compliance with FPGA/DSP power-up timing specifications.
Availability
NCP3121MNTXG is available at Aetrix Electronics and suitable for FPGA power delivery, DSP multi-rail systems, and medical imaging signal chain applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for NCP3121MNTXG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Nasdaq: ON) is a global semiconductor leader delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NCP3121MNTXG belongs to onsemi's high-efficiency DC/DC converter product line, engineered specifically for space-constrained, multi-voltage embedded systems where precise sequencing, thermal robustness, and dual-rail integration reduce system-level complexity.
FAQ
What is the maximum supported switching frequency for NCP3121MNTXG?
The NCP3121MNTXG supports an adjustable switching frequency range of 200 kHz to 750 kHz, set by an external resistor connected from the RT pin to AGND. At 25°C and with RT = 52.3 kΩ, the typical frequency is 635 kHz; the upper limit is guaranteed across temperature (−40°C to +125°C) per the datasheet's electrical characteristics table.
Does NCP3121MNTXG support independent enable/disable of each channel?
Yes, the NCP3121MNTXG provides fully independent enable control via EN1 (Pin 22) and EN2 (Pin 20). Each pin accepts a logic-high signal (>2.0 V) to activate its respective channel and logic-low (<0.8 V) to disable it. Internal pull-up current is 4.0 µA, enabling direct interface with microcontroller GPIOs without external biasing.
How does the auto-tracking feature work on NCP3121MNTXG?
The NCP3121MNTXG implements auto-tracking using TRACK1 (Pin 18) and TRACK2 (Pin 17). When configured in tracking mode, the second channel's output ramps in proportion to the first-enabling monotonic, aligned voltage rise for FPGA core/I/O rails. The tracking offset is tightly controlled at ±15 mV, and the TRACK pins accept external voltage sources to define custom slew rates.
What thermal protection mechanisms does NCP3121MNTXG include?
The NCP3121MNTXG incorporates thermal shutdown with a trip point of 160°C (typical) and 15°C hysteresis. When junction temperature exceeds this threshold, the device immediately disables both channels, reduces supply current to ~5 mA, and holds shutdown until temperature falls below 145°C-then automatically restarts with soft-start. This protects against sustained overload or inadequate heatsinking.
Can NCP3121MNTXG operate with ceramic output capacitors only?
Yes, the NCP3121MNTXG is explicitly designed to be stable with low-ESR ceramic output capacitors-no electrolytic or tantalum capacitors are required. Its compensation architecture and error amplifier characteristics ensure phase margin >45° across load and input variations when using standard X5R/X7R MLCCs, enabling compact, high-reliability, and long-lifetime power designs.
NCP3121MNTXG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 13.2V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 11.88V
- Current - Output:
- 3A
- Frequency - Switching:
- 200kHz ~ 750kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
NCP3121MNTXG FAQ
1.How can I place an order for NCP3121MNTXG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP3121MNTXG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP3121MNTXG reliable?
The price and inventory of NCP3121MNTXG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP3121MNTXG is usually 5 days.
3.What payment methods are accepted for NCP3121MNTXG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP3121MNTXG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP3121MNTXG?
NCP3121MNTXG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP3121MNTXG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP3121MNTXG?
For technical support, including NCP3121MNTXG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP3121MNTXG requirements.
6.How does Aetrix verify that NCP3121MNTXG is sourced from the original manufacturer or authorized distributors?
All NCP3121MNTXG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP3121MNTXG meets industry standards.
7.What is the process for return or replacement of NCP3121MNTXG?
All NCP3121MNTXG units undergo pre-shipment inspection (PSI). If there is an issue with NCP3121MNTXG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP3121MNTXG part is unused and in its original packaging.
Return procedure for NCP3121MNTXG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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