onsemi NCP3133AMNTXG

Overview

NCP3133AMNTXG from onsemi is a fully integrated synchronous buck converter delivering up to 3 A continuous output current for 3.3 V and 5 V step-down applications. It operates across a 2.9 V–5.5 V input range, supports 0.6 V–0.84×VIN adjustable output voltage, and features voltage-mode control with 1.1 MHz fixed-frequency operation in FCCM mode. It serves as the primary DC-DC power stage in compact, high-efficiency point-of-load supplies for FPGA I/O rails and microcontroller core logic.

For engineers reviewing the NCP3133AMNTXG datasheet, pinout, applications, or equivalent options, key selection criteria include its dual-mode operation (FCCM vs. automatic CCM/DCM), integrated power-good indicator, pre-bias startup capability, thermal shutdown at 135 °C, and QFN-16 3 mm × 3 mm package with exposed thermal pad.

Technical Context

The NCP3133AMNTXG implements voltage-mode PWM control with internal 600 mV reference (±1% tolerance) and adaptive soft-start (400 µs ramp). Its dual-mode architecture uses the PS pin to select between forced continuous conduction mode (FCCM) - delivering fixed 1.1 MHz switching and tight regulation - or automatic CCM/DCM mode, where zero-crossing detection enables frequency reduction at light load to sustain >90% efficiency down to 100 mA.

Protection logic includes cycle-by-cycle over-current limiting on both high-side (4.8 A typical trip) and low-side (5.1 A latch-off), ±17% window-based power-good monitoring with 400 µs delay, UVLO thresholds of 2.8 V (VIN/VDD) with hysteresis, and thermal shutdown at 135 °C with 40 °C hysteresis. Output discharge is enabled via internal 20 Ω transistor during fault or disable.

Key Specifications

Pinout & Package

The NCP3133AMNTXG is housed in a thermally enhanced 3 mm × 3 mm, 16-pin QFN package (Case 485DA) with an exposed thermal pad requiring solder connection to PGND for optimal thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with MP2315DJ-LF-Z and TPS54331DR, the NCP3133AMNTXG delivers integrated power-good signaling, pre-bias startup, and automatic light-load efficiency optimization in a compact 3 mm × 3 mm QFN - making it optimal for space-constrained, high-reliability embedded systems requiring deterministic power sequencing.

Availability

NCP3133AMNTXG is available at Aetrix Electronics and suitable for industrial PLC I/O modules, FPGA configuration rails, automotive infotainment SoC cores, and USB-C PD sink power paths requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for NCP3133AMNTXG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and IoT applications.

The NCP3133AMNTXG belongs to onsemi's integrated DC-DC converter product line, designed specifically for high-efficiency, low-voltage point-of-load regulation in space- and thermal-constrained embedded systems.

FAQ

What is the recommended input voltage range for stable operation of the NCP3133AMNTXG?

The NCP3133AMNTXG operates reliably across a 2.9 V to 5.5 V input voltage range. This range supports common sources including single-cell Li-ion batteries (3.0–4.2 V), USB 5 V ports, and regulated 3.3 V industrial rails. Operation below 2.9 V triggers VIN UVLO (2.8 V threshold), while exceeding 5.5 V risks absolute maximum rating violation. For best efficiency at 3.3 V output, 3.3 V or 5.0 V input is recommended per datasheet characterization.

Does the NCP3133AMNTXG support pre-bias startup, and how does it function?

Yes, the NCP3133AMNTXG supports pre-bias startup. When the output capacitor is pre-charged, the device holds the low-side MOSFET off until the internal soft-start reference voltage ramps above the FB pin voltage. This prevents reverse current flow and protects sensitive downstream loads. The feature is active in both FCCM and automatic CCM/DCM modes and requires no external components - confirmed in the Detailed Description section of the datasheet.

What is the purpose of the PS pin on the NCP3133AMNTXG, and how should it be configured?

Pin 8 (PS) selects the NCP3133AMNTXG's operating mode: connecting it to GND via ≤174 kΩ enables automatic CCM/DCM mode for light-load efficiency, while leaving it floating or pulling it high (to VDD) selects forced continuous conduction mode (FCCM) for fixed 1.1 MHz switching and consistent EMI profile. The PS pin sources 10 µA, so resistor selection must ensure voltage drop stays below 2.2 V to guarantee mode recognition - verified in Table 5 and the Operation Mode section.

How does the power-good (PGD) signal behave during startup and fault conditions for the NCP3133AMNTXG?

The NCP3133AMNTXG's PGD pin is an open-drain output that asserts high only when the FB voltage remains within ±17% of 600 mV for ≥400 µs. During startup, PGD stays low until regulation is achieved and held. It de-asserts immediately upon EN low, VDD UVLO, or FB excursion outside the window - with 10 µs fault response latency. A 400 µs delay ensures stable regulation before system release, and the 5 mA sink capability allows direct interfacing with microcontroller reset inputs.

What thermal management considerations apply to the NCP3133AMNTXG in high-power applications?

The NCP3133AMNTXG has a junction-to-ambient thermal resistance of 45 °C/W and thermal shutdown at 135 °C with 40 °C hysteresis. To maintain reliability at 3 A continuous load, the exposed thermal pad must be soldered to a minimum 200 mm² copper pour connected to PGND using ≥4 thermal vias. Layout guidelines specify separating AGND and PGND planes and connecting them at a single point near the IC. Efficiency data shows >94% at full load (3.3 V in, 1.5 V out), limiting power dissipation to <180 mW - enabling operation without heatsink in most 0–70 °C environments.