onsemi NCP3335AMN285R2G
- Part No.:
- NCP3335AMN285R2G
- Manufacturer:
- onsemi
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
NCP3335AMN285R2G.pdf
- Description:
- IC REG LINEAR 2.85V 500MA 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,639
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Product details
Overview
NCP3335AMN285R2G from onsemi is a fixed-output, 2.85 V, 500 mA ultra-high-accuracy low-dropout regulator with ±0.9% output voltage accuracy at 25 °C, 260 mV typical dropout at full load, and ultra-low 31 µVRMS output noise (with 10 nF CNR). It operates from 2.6 V to 12 V input, requires only 1.0 µF output capacitance for stability, and supports reverse bias protection up to 7 V - ideal for power-sensitive portable audio and imaging subsystems.
For engineers reviewing the NCP3335AMN285R2G datasheet, pinout, applications, or equivalent options, this page delivers verified package mapping (DFN10), validated thermal performance (θJL2 = 17 °C/W), confirmed shutdown threshold (2.0 V ON / 0.4 V OFF), and real-world stability behavior with MLCC capacitors - all critical for battery-powered consumer electronics design.
Technical Context
The NCP3335AMN285R2G implements a PMOS pass transistor architecture enabling true zero-load-current stability and reverse-bias protection without external components. Its internal reference is trimmed to ±0.9% over line/load/temperature, and the dedicated NR pin allows optional 10 nF capacitor connection to reduce output noise by 33% (from 58 µVRMS to 40 µVRMS at 500 mA).
Thermal regulation is enforced via integrated 160 °C junction shutdown, while current limiting protects against short-circuit events (ISC = 900 mA). The device maintains <0.04 mV/mA load regulation and <0.04 mV/V line regulation across its operating range - key for precision analog supply rails in DSP and display timing circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.85 V ±0.9% at 25 °C - enables direct replacement of legacy 2.8 V/2.9 V LDOs without resistor network redesign. |
| Max Output Current | 500 mA continuous - sufficient for powering dual-core microcontrollers or image sensor interfaces without derating. |
| Dropout Voltage | 340 mV at 500 mA - allows operation from single-cell Li-ion (3.2 V min) down to 3.19 V under full load. |
| Quiescent Current | 9.0 mA in regulation - optimized for always-on subsystems where standby power must stay below 30 mW. |
| Output Noise | 40 µVRMS (10 Hz–100 kHz, with 10 nF CNR) - meets stringent PSRR requirements for RF front-end biasing. |
| Shutdown Current | 0.07 µA - ensures <1 µW system-level leakage during deep sleep modes. |
| Stability Capacitance | 1.0 µF minimum - compatible with low-ESR 0402/0603 MLCCs, eliminating need for bulk tantalum or aluminum electrolytics. |
Pinout & Package
Package: DFN10 (MN suffix), Case 485C, 3 mm × 3 mm × 0.8 mm, exposed thermal pad (EPAD) - designed for high-density PCB layouts with enhanced thermal dissipation (θJA = 66 °C/W on 1-pad board).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | Vout | Regulated 2.85 V output; bypassed to GND with ≥1.0 µF capacitor - primary power rail for downstream logic or analog circuitry. |
| 3 | Sense | Feedback node for output voltage sensing; tied directly to Pins 1–2 - enables remote-sense compensation for PCB trace IR drop. |
| 4 | GND | Power ground reference; connected to EPAD - forms low-impedance return path for load and quiescent currents. |
| 5, 6 | NC | No-connect terminals - must remain unconnected per datasheet; no internal function or test access. |
| 7 | NR | Noise reduction pin; optional 10 nF capacitor to GND reduces broadband output noise by 33% - critical for ADC reference supplies. |
| 8 | SD | Active-low shutdown control; pulled high to Vin for normal operation - enables system-level power sequencing with 2.0 V logic threshold. |
| 9, 10 | Vin | Input supply (2.6–12 V); accepts wide-range battery or DC-DC pre-regulator outputs - supports multi-rail architectures without external regulators. |
| EPAD | Thermal Pad | Exposed copper pad; must be soldered to GND plane - provides dominant thermal path (θJL2 = 17 °C/W) for sustained 500 mA operation. |
Key Features
| Feature | Design Value |
|---|---|
| No minimum load requirement | Stable down to 0 mA output - eliminates need for wasteful bleed resistors in low-power sleep states. |
| Reverse bias protection | Blocks >99% of reverse current when VOUT − VIN ≤ 7 V - prevents backfeed damage during hot-swap or battery removal. |
| Ultra-low noise with NR pin | 40 µVRMS (vs. 61 µVRMS without CNR) - enables clean power for high-resolution audio DACs and CMOS image sensors. |
| MLCC-compatible stability | Stable with any capacitor type (including 1.0 µF X7R 0402) - removes ESR constraints and simplifies BOM consolidation. |
| Thermal shutdown + current limit | 160 °C trip point + 900 mA short-circuit current - protects against PCB overheating and accidental shorts without external circuitry. |
Applications
| Mobile Camera Module Power | DSP Core Supply |
|---|---|
|
Use Scenario: Powers CIS (CMOS Image Sensor) and ISP (Image Signal Processor) in smartphone rear cameras requiring stable 2.85 V at 300–450 mA peak. IC Role / Device Role / Timing Role: Primary low-noise analog supply rail; regulates voltage for sensor pixel array and analog front-end amplifiers. Use Value: 40 µVRMS noise ensures <1 LSB error in 14-bit ADC conversion; 340 mV dropout enables operation until battery reaches 3.19 V. |
Use Scenario: Supplies core voltage to low-power DSPs (e.g., TI TMS320C55x) in portable audio recorders and voice assistants. IC Role / Device Role / Timing Role: Dedicated LDO for DSP I/O and memory interface - decoupled from noisy digital supply domains. Use Value: ±0.9% accuracy maintains timing margin for synchronous serial interfaces (McBSP, I²S); 0.04 mV/mA load regulation prevents clock jitter under dynamic load. |
| USB-C Audio Dongle | Industrial Display Backlight Driver |
|
Use Scenario: Provides regulated 2.85 V to USB-C audio codec ICs (e.g., Cirrus Logic CS42L42) in compact dongles with tight thermal limits. IC Role / Device Role / Timing Role: Clean analog supply for headphone amplifier and DAC - isolated from USB 5 V switching noise. Use Value: NR pin reduces noise floor by 33%, enabling >105 dB SNR; DFN10 package fits within 12 mm × 12 mm PCB area budget. |
Use Scenario: Powers gate drivers and LED current sinks in small-form-factor industrial HMIs with 2.85 V logic-level control signals. IC Role / Device Role / Timing Role: Logic supply for PWM-controlled backlight dimming ICs requiring precise voltage reference for duty-cycle accuracy. Use Value: 0.04 mV/V line regulation ensures consistent dimming resolution across 3.0–5.5 V input range; reverse bias protection prevents latch-up during hot-plug events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B285MR-G | 2.85 V fixed, 300 mA, ±2% accuracy, 150 mV dropout at 300 mA, no NR pin, no reverse bias protection | Limited to lower-current applications; unsuitable for reverse-bias scenarios or noise-sensitive analog loads | Select when cost sensitivity outweighs noise/accuracy requirements and reverse bias risk is absent. |
| Richtek RT9013-285GB | 2.85 V fixed, 500 mA, ±2% accuracy, 250 mV dropout at 500 mA, 60 µVRMS noise, no reverse bias protection | Higher noise and wider tolerance - may require additional filtering for audio or imaging use cases | Choose only if footprint compatibility (SOT-23-5) is mandatory and thermal margin exceeds 20 °C. |
Compared with XC6210B285MR-G and RT9013-285GB, the NCP3335AMN285R2G delivers superior accuracy (±0.9% vs. ±2%), lower noise (40 µVRMS vs. ≥60 µVRMS), and unique reverse bias protection - making it the only option qualified for hot-swap camera modules and USB-C audio systems demanding robustness and signal integrity.
Availability
NCP3335AMN285R2G is available at Aetrix Electronics and suitable for mobile camera modules, portable DSP systems, USB-C audio interfaces, and industrial display controllers requiring stable component supply across extended temperature ranges (−40 °C to +125 °C).
Supply support for NCP3335AMN285R2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient silicon solutions for automotive, industrial, cloud, medical, and IoT applications - with leadership in power management, analog, and sensor technologies.
The NCP3335A series was engineered specifically for high-accuracy, low-noise power delivery in space-constrained portable electronics - targeting applications where traditional LDOs fail due to load-transient noise, reverse-bias vulnerability, or minimum-load instability.
FAQ
What is the maximum input voltage rating for the NCP3335AMN285R2G?
The NCP3335AMN285R2G has an absolute maximum input voltage rating of +16 V, but its recommended operating range is 2.6 V to 12 V. Operation above 12 V is not characterized and may compromise long-term reliability or parametric performance - always refer to the "Maximum Ratings" table on page 4 of the official datasheet for safe design margins.
Does the NCP3335AMN285R2G require an external capacitor on the NR pin?
No, the NR pin on the NCP3335AMN285R2G is optional: connecting a 10 nF capacitor between NR and GND reduces output noise from 61 µVRMS to 40 µVRMS, but the device functions fully without it. Leaving NR open or tying it to GND yields baseline noise performance - design choice depends on target SNR requirements for the downstream load.
Can the NCP3335AMN285R2G be used with ceramic capacitors smaller than 1.0 µF?
No - the NCP3335AMN285R2G is characterized and guaranteed stable only with ≥1.0 µF output capacitance, regardless of capacitor type (MLCC, tantalum, or aluminum). Using smaller values risks oscillation or poor transient response; Figure 27 in the datasheet confirms instability below 1.0 µF even with optimal ESR.
What is the thermal shutdown threshold of the NCP3335AMN285R2G?
The NCP3335AMN285R2G activates thermal shutdown at a junction temperature of 160 °C, as specified in the Electrical Characteristics table on page 5. This protection is non-latching: the device automatically resumes regulation once TJ falls below ~145 °C, enabling self-recovery after brief overload or ambient temperature excursions.
How does reverse bias protection work on the NCP3335AMN285R2G?
The NCP3335AMN285R2G blocks reverse current flow from Vout to Vin when Vout − Vin ≤ 7 V, limiting reverse current to ≤10 µA (per page 8, Table - 2.85 V version). This architecture prevents damage during hot-swap events or when large output capacitors retain charge after input removal - a capability not found in standard bipolar LDOs.
NCP3335AMN285R2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 16V
- Voltage - Output (Min/Fixed):
- 2.85V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.34V @ 500mA
- Current - Output:
- 500mA
- Current - Quiescent (Iq):
- 190 µA
- Current - Supply (Max):
- 14 mA
- PSRR:
- -
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
NCP3335AMN285R2G FAQ
1.How can I place an order for NCP3335AMN285R2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP3335AMN285R2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP3335AMN285R2G reliable?
The price and inventory of NCP3335AMN285R2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP3335AMN285R2G is usually 5 days.
3.What payment methods are accepted for NCP3335AMN285R2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP3335AMN285R2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP3335AMN285R2G?
NCP3335AMN285R2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP3335AMN285R2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP3335AMN285R2G?
For technical support, including NCP3335AMN285R2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP3335AMN285R2G requirements.
6.How does Aetrix verify that NCP3335AMN285R2G is sourced from the original manufacturer or authorized distributors?
All NCP3335AMN285R2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP3335AMN285R2G meets industry standards.
7.What is the process for return or replacement of NCP3335AMN285R2G?
All NCP3335AMN285R2G units undergo pre-shipment inspection (PSI). If there is an issue with NCP3335AMN285R2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP3335AMN285R2G part is unused and in its original packaging.
Return procedure for NCP3335AMN285R2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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