onsemi NCP361MUTBG
- Part No.:
- NCP361MUTBG
- Manufacturer:
- onsemi
- Category:
- Mixed Technology
- Package:
- 6-UDFN Exposed Pad
- Datasheet:
-
NCP361MUTBG.pdf
- Description:
- TVS DEVICE MIXED 6-UDFN
- Quantity:
- Payment:

- Shipping:

Inventory:8,727
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP361MUTBG from onsemi is a USB-positive overvoltage protection controller with integrated PMOS FET, 5.675 V overvoltage lockout (OVLO), 3.0 V undervoltage lockout (UVLO), and 750 mA overcurrent protection. It delivers <200 mV dropout at 500 mA and features an open-drain FLAG output for fault reporting in portable USB-powered systems.
For engineers reviewing the NCP361MUTBG datasheet, pinout, applications, or equivalent options, this device supports rapid fault detection (<1.5 µs output turn-off), thermal shutdown at 150 °C, and IEC61000-4-2 Level 4 ESD protection - critical for USB interface robustness in mobile and peripheral designs.
Technical Context
The NCP361MUTBG implements dual voltage monitoring: UVLO (2.85–3.15 V) ensures safe startup only above valid supply levels, while OVLO (5.43–5.9 V) triggers immediate PMOS gate disablement to isolate downstream circuitry. Its internal PMOS provides bidirectional current path control without external components.
Overcurrent protection operates at 550–950 mA with automatic hiccup-mode recovery, and thermal shutdown (150 °C ±30 °C hysteresis) prevents latch-up during sustained overload. The FLAG pin asserts low on any fault condition - OVLO, UVLO, OCP, or thermal - enabling host MCU coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| OVLO Threshold | 5.675 V typical; disconnects output within 1.5 µs when input exceeds this level to protect 5 V USB loads from overvoltage damage. |
| UVLO Threshold | 3.0 V typical; prevents operation below minimum valid USB supply, ensuring stable enablement only when VBUS is properly established. |
| Overcurrent Limit | 750 mA typical; limits charge/battery current to prevent system overload and enables hiccup-mode recovery to avoid thermal runaway. |
| Dropout Voltage | 200 mV max at 500 mA; minimizes power loss and voltage sag across internal PMOS, preserving regulated output under full load. |
| FLAG Output | Open-drain, low-active; signals faults (OVLO/UVLO/OCP/thermal) to host MCU with ≤400 mV low-level voltage at 1 mA sink current. |
| ESD Protection | ±15 kV air / ±8 kV contact per IEC61000-4-2 Level 4; protects IN pin against electrostatic discharge without external TVS diodes. |
| Quiescent Current | 35 µA typical; enables ultra-low standby power consumption in always-on USB ports and battery-backed peripherals. |
Pinout & Package
Package: UDFN6 (2 mm × 2 mm, 0.65 mm pitch), Pb-free, exposed thermal pad (Case 517AB). Thermal resistance RJA = 240 °C/W with recommended PCB copper area.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN | Enable input | Active-low logic control: tie to GND for normal operation; high disables output regardless of fault state. |
| 2 - GND | Power ground | Reference node for all internal circuits and thermal pad connection point for heat dissipation. |
| 3 - IN | Input power | Accepts 1.2–20 V VBUS; requires ≥1 µF low-ESR ceramic capacitor to GND for ESD and transient filtering. |
| 4,5 - OUT | Output power | Dual parallel pins for 600 mA DC current delivery; must be shorted externally to common load rail. |
| 6 - FLAG | Fault indicator | Open-drain output pulled low on any fault; requires external pull-up resistor (10 kΩ–1 MΩ) to VCC for proper logic signaling. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PMOS FET | Eliminates need for external MOSFET and gate driver, reducing BOM count and PCB footprint by >30% in USB port protection designs. |
| Hiccup-mode OCP | Automatically cycles ON/OFF during overcurrent events to limit average power dissipation and prevent thermal damage without latching. |
| UVLO + OVLO dual threshold | Ensures clean power sequencing: blocks startup until VBUS reaches 3.0 V, then cuts off before exceeding 5.675 V - preventing brown-out and overvoltage simultaneously. |
| Thermal shutdown with hysteresis | Shuts down at 150 °C and re-enables only after cooling to 120 °C, avoiding oscillation near thermal limit during sustained overload. |
| IEC61000-4-2 Level 4 compliance | Validated for ±15 kV air / ±8 kV contact ESD immunity on IN pin - meets industrial and consumer USB interface reliability requirements. |
Applications
| USB Mobile Charging Port | USB Peripheral Interface |
|---|---|
|
Use Scenario: Protecting smartphone or tablet USB ports from accidental 9–20 V adapter misconnection or faulty chargers. IC Role / Device Role / Timing Role: Primary overvoltage guard between VBUS and system power rail; responds within 1.5 µs to disconnect load. Use Value: Prevents permanent damage to USB PHY, PMIC, and battery charging ICs by clamping input before destructive energy transfers. |
Use Scenario: Securing USB-powered peripherals (keyboards, mice, hubs) against reverse-connected or non-compliant hosts. IC Role / Device Role / Timing Role: Input-side protector that isolates downstream logic from upstream VBUS anomalies using internal PMOS switch. Use Value: Enables plug-and-play interoperability without requiring custom firmware checks or external protection diodes. |
| Portable Media Player Power Path | Set-Top Box USB Host Port |
|
Use Scenario: Managing power delivery to MP3 players or Bluetooth speakers connected to automotive or wall adapters. IC Role / Device Role / Timing Role: Overvoltage + overcurrent supervisor controlling power path to Li-ion battery charger and audio subsystem. Use Value: Maintains uninterrupted playback during transient surges while flagging faults to system MCU for graceful shutdown or alert. |
Use Scenario: Hardening USB host ports on STBs against hot-plug ESD events and unregulated third-party accessories. IC Role / Device Role / Timing Role: Front-end protection element placed directly at USB connector, providing first-line defense before USB transceiver. Use Value: Reduces field failure rate due to connector ESD by meeting IEC61000-4-2 Level 4 without additional discrete TVS devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar overvoltage protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TUSB542IRWBR | Dual-lane USB 3.1 re-driver with integrated 5.5 V OVLO; no internal PMOS switch or FLAG output. | Designed for signal integrity enhancement, not power path protection; lacks overcurrent or thermal shutdown. | Select only if signal retiming is required alongside basic OVLO - not a functional replacement for NCP361MUTBG's power-switching role. |
| TPD3S014TDCR | USB port protector with 5.7 V OVLO, 1.2 A OCP, and integrated 15 kV ESD diodes; uses external PMOS control. | Requires external MOSFET and gate driver; larger solution size but higher current rating and adjustable OCP via resistor. | Choose when >750 mA load current or programmable OCP threshold is needed; adds complexity but increases flexibility. |
Compared with TUSB542IRWBR and TPD3S014TDCR, the NCP361MUTBG uniquely integrates both PMOS switch and fault-flag logic in a 2×2 mm UDFN package, delivering complete single-chip USB power path protection without external active components - ideal for space-constrained portable designs.
Availability
NCP361MUTBG is available at Aetrix Electronics and suitable for USB mobile charging ports, peripheral interfaces, portable media players, set-top box host ports, and automotive infotainment USB hubs requiring stable component supply and long-term lifecycle support.
Supply support for NCP361MUTBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, and sensor solutions for automotive, industrial, and consumer markets.
The NCP361MUTBG belongs to onsemi's USB interface protection product line, engineered specifically to simplify robust VBUS conditioning in portable and embedded USB applications with minimal external components.
FAQ
What is the overvoltage lockout (OVLO) threshold of the NCP361MUTBG?
The NCP361MUTBG has a typical overvoltage lockout threshold of 5.675 V, with a min/max range of 5.43 V to 5.9 V. This threshold triggers immediate disconnection of the internal PMOS FET to protect downstream circuitry when input voltage exceeds the limit. The device also includes 100 mV hysteresis to prevent chatter during transient overvoltage events. The NCP361MUTBG maintains this specification across its full operating temperature range of −40 °C to +85 °C.
Does the NCP361MUTBG require external components to function?
The NCP361MUTBG requires only two external capacitors: a ≥1 µF low-ESR ceramic capacitor between IN and GND, and another ≥1 µF capacitor on the OUT pins. An external pull-up resistor (10 kΩ–1 MΩ) on the FLAG pin is mandatory due to its open-drain configuration. No external MOSFET, gate driver, or voltage reference is needed - the internal PMOS FET and all protection circuitry are fully integrated. The NCP361MUTBG is designed for minimal external component count in USB power path applications.
How does the FLAG output of the NCP361MUTBG behave during fault conditions?
The FLAG output of the NCP361MUTBG is an open-drain, active-low signal that pulls low during any fault: overvoltage (IN > OVLO), undervoltage (IN < UVLO), overcurrent (ILOAD > ILIM), or thermal shutdown (TJ > 150 °C). It remains low until all fault conditions clear and the device recovers. The NCP361MUTBG specifies ≤400 mV low-level voltage at 1 mA sink current, and requires an external pull-up resistor to VCC for proper logic-level interpretation by the host MCU.
What package type is used for the NCP361MUTBG?
The NCP361MUTBG uses the UDFN6 (2 mm × 2 mm, 0.65 mm pitch) package, designated Case 517AB, with an exposed thermal pad for enhanced heat dissipation. It is Pb-free and RoHS-compliant. This compact 6-pin package supports RJA = 240 °C/W with proper PCB copper area, enabling reliable 600 mA continuous operation. The NCP361MUTBG pinout differs from the TSOP-5 variant (e.g., NCP361SNT1G), with dual OUT pins and relocated EN/FLAG positions.
Can the NCP361MUTBG be used in automotive applications?
The NCP361MUTBG is rated for industrial temperature range (−40 °C to +85 °C) and is not AEC-Q100 qualified. For automotive applications, onsemi offers the NCV361SNT1G - an automotive-grade variant with identical functionality, AEC-Q100 qualification, and PPAP capability. The NCP361MUTBG is intended for consumer, computing, and industrial USB applications where extended temperature or automotive qualification is not required. Always verify ambient and junction temperature margins in final layout when using the NCP361MUTBG in demanding environments.
NCP361MUTBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 6-UDFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Voltage - Clamping:
- -
- Technology:
- Mixed Technology
- Number of Circuits:
- 1
- Applications:
- General Purpose
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-UDFN (2x2)
NCP361MUTBG FAQ
1.How can I place an order for NCP361MUTBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP361MUTBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP361MUTBG reliable?
The price and inventory of NCP361MUTBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP361MUTBG is usually 5 days.
3.What payment methods are accepted for NCP361MUTBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP361MUTBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP361MUTBG?
NCP361MUTBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP361MUTBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP361MUTBG?
For technical support, including NCP361MUTBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP361MUTBG requirements.
6.How does Aetrix verify that NCP361MUTBG is sourced from the original manufacturer or authorized distributors?
All NCP361MUTBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP361MUTBG meets industry standards.
7.What is the process for return or replacement of NCP361MUTBG?
All NCP361MUTBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP361MUTBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP361MUTBG part is unused and in its original packaging.
Return procedure for NCP361MUTBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP361MUTBG Tags

-
ESD03A5V5R17V
Stackpole Electronics Inc

-
ESDU02A5V5R17V
Stackpole Electronics Inc
-
0603ESDA-MLP7
Eaton - Electronics Division
.jpg)
-
0603ESDA2-TR2
Eaton - Electronics Division

-
PS04LTVA1
Eaton - Electronics Division
.jpg)
-
0402ESDA-MLP1
Eaton - Electronics Division
.jpg)
-
0402ESDA-MLP7
Eaton - Electronics Division

-
TPD2S017DBVR
Texas Instruments
.jpg)
-
V2F105A150Y2EDP
KYOCERA AVX

-
82307050029
Würth Elektronik
-
NCP360SNT1G
onsemi
.jpg)
-
V2F118A400Y2EDP
KYOCERA AVX
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

