onsemi NCP4671DMX15TCG
- Part No.:
- NCP4671DMX15TCG
- Manufacturer:
- onsemi
- Package:
- 6-XFDFN
- Datasheet:
-
NCP4671DMX15TCG.pdf
- Description:
- IC REG LINEAR 1.5V 400MA 6XDFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,803
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Product details
Overview
NCP4671DMX15TCG from onsemi is a dual-rail ultra-low dropout linear regulator delivering a fixed 1.5 V output at up to 400 mA, with 180 mV typical dropout at full load, ±15 mV output accuracy at 25°C, and bias-input separation enabling operation down to 0.9 V input. It serves as a precision low-voltage power stage for core logic in portable battery-powered systems.
For engineers reviewing the NCP4671DMX15TCG datasheet, pinout, applications, or equivalent options, this page provides verified package mapping (XDFN6), validated dual-rail architecture details, confirmed thermal performance (RJA = 250°C/W), and real-world transient response data for fast-switching SoC supply domains.
Technical Context
The NCP4671DMX15TCG implements a CMOS-based dual-rail LDO architecture: VIN supplies the pass transistor path while VBIAS independently powers the control circuitry, decoupling regulation stability from input rail noise and enabling sub-1 V operation. This separation yields high PSRR (80 dB at 1 kHz on VIN, 50 dB on VBIAS) and supports tight output voltage tolerance across temperature.
It features an active chip-enable (CE) input with internal pull-down, auto-discharge functionality via integrated N-channel output discharge transistor (D-version), and current-foldback protection limiting short-circuit current to 120 mA. The device operates across −40°C to +85°C ambient with guaranteed 1.5 V output accuracy of ±20 mV over full temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.5 V ±15 mV at 25°C; ±20 mV over −40°C to +85°C - ensures stable core voltage for 1.5 V I/O or memory interfaces |
| Max Output Current | 400 mA continuous - sufficient for powering ARM Cortex-M cores, FPGA I/O banks, or sensor signal chains |
| Dropout Voltage | 180 mV typical at 400 mA - enables regulation from 1.68 V input, critical for post-buck DC/DC stages |
| Quiescent Current | 28 µA typical - minimizes standby power loss in always-on subsystems like RTC or wake-up controllers |
| PSRR | 80 dB at 1 kHz (VIN ripple), 50 dB at 1 kHz (VBIAS ripple) - suppresses switching noise from upstream converters |
| Thermal Resistance | RJA = 250°C/W (XDFN6) - requires minimal PCB copper area for thermal management in space-constrained layouts |
| Enable Threshold | VCEH = 0.8 V min, VCEL = 0.3 V max - compatible with 1.8 V and 3.3 V logic-level control signals |
Pinout & Package
XDFN6 package: 1.2 mm × 1.2 mm × 0.4 mm ultra-thin leadless封装 with wettable flanks; 6-pin layout optimized for high-density portable PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VBIAS) | Bias supply input | Powers internal control circuitry; must be ≥ VOUT + 1.6 V (≥3.1 V for 1.5 V version); isolates regulation loop from VIN noise |
| 2 (GND) | Analog/digital ground reference | Common return for VIN, VBIAS, CE, and VOUT; requires low-impedance connection to minimize PSRR degradation |
| 3 (CE) | Chip enable input | Active-high logic control; internal 1 µA pull-down allows direct tie to VBIAS if unused; enables system-level power sequencing |
| 4 (VIN) | Main power input | Supplies pass transistor; operates from 0.9 V to VBIAS; minimum headroom = VOUT + 0.1 V (1.6 V for 1.5 V output) |
| 5 (NC) | No-connect terminal | Not internally bonded; must remain unconnected per datasheet; no routing or thermal relief required |
| 6 (VOUT) | Regulated output | Delivers 1.5 V at up to 400 mA; includes integrated discharge FET (D-version) for rapid VOUT collapse during disable |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail architecture | Separate VBIAS and VIN inputs eliminate control-loop dependency on noisy main rail, enabling stable low-VIN operation |
| Auto-discharge function | Integrated N-channel discharge transistor pulls VOUT to GND within microseconds upon CE deactivation - prevents floating outputs in multi-rail systems |
| Ultra-low quiescent current | 28 µA typical enables >1-year battery life in coin-cell–powered devices with periodic wake-up cycles |
| High-accuracy output | ±15 mV initial tolerance and ±50 ppm/°C tempco ensure consistent timing margin for 1.5 V DDR I/O or SerDes reference rails |
| Low-noise regulation | 70 µVRMS output noise (10 Hz–100 kHz) preserves SNR in analog front-ends and RF bias networks |
Applications
| Mobile Application Processor Core Supply | Wearable Sensor Hub Power |
|---|---|
Use Scenario: Powers ARM Cortex-M4/M7 core logic in compact wearable devices where battery voltage drops below 2.0 V during discharge. IC Role / Device Role / Timing Role: Primary 1.5 V core LDO delivering tightly regulated voltage to processor VDDCORE pins with fast load transient response. Use Value: 180 mV dropout enables >90% battery utilization; 400 mA capacity supports burst-mode CPU operation without brownout. |
Use Scenario: Supplies 1.5 V to MEMS accelerometer, gyroscope, and BLE radio subsystems in hearables with shared Li-ion cell. IC Role / Device Role / Timing Role: Low-noise, low-quiescent LDO providing clean power to analog sensor interfaces and RF transceivers. Use Value: 70 µVRMS noise avoids signal corruption; 28 µA IQ extends runtime between firmware updates. |
| Industrial IoT Edge Node I/O Rail | Automotive Camera Module Bias |
Use Scenario: Generates 1.5 V for FPGA I/O banks interfacing with RS-485 transceivers and isolated ADCs in remote monitoring nodes. IC Role / Device Role / Timing Role: Stable, PSRR-optimized LDO ensuring signal integrity across wide temperature range (−40°C to +85°C). Use Value: 80 dB PSRR rejects switching noise from adjacent DC/DC converters; ±20 mV accuracy maintains interface timing margins. |
Use Scenario: Provides 1.5 V bias to image sensor analog front-end and ISP power domain in automotive rear-view cameras. IC Role / Device Role / Timing Role: High-reliability LDO with auto-discharge supporting ASIL-B–compliant power sequencing and fail-safe shutdown. Use Value: Integrated discharge FET ensures rapid VOUT collapse during ignition-off, preventing latch-up in downstream imaging ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-dropout LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B152MR-G | Single-rail 1.5 V LDO; 250 mV dropout at 400 mA; no VBIAS pin; 30 µA IQ | Lacks dual-rail architecture and auto-discharge; lower PSRR (65 dB @ 1 kHz) | Choose when board space is constrained and VBIAS isolation is unnecessary; verify thermal derating at 400 mA |
| Richtek RT9013-15GB | Single-rail 1.5 V LDO; 200 mV dropout at 300 mA; 25 µA IQ; no discharge FET | Lower max current (300 mA vs. 400 mA); no integrated output discharge; smaller SOT-23-5 footprint | Prefer for cost-sensitive designs with <300 mA loads and no requirement for rapid VOUT discharge |
Compared with XC6210B152MR-G and RT9013-15GB, the NCP4671DMX15TCG uniquely delivers dual-rail operation for enhanced noise immunity, guaranteed 400 mA output with 180 mV dropout, and integrated auto-discharge-critical for sequenced power-down in multi-rail embedded systems.
Availability
NCP4671DMX15TCG is available at Aetrix Electronics and suitable for mobile processor core supplies, wearable sensor hubs, industrial IoT edge node I/O rails, and automotive camera module bias requiring stable component supply, Pb-free compliance, and XDFN6 footprint compatibility.
Supply support for NCP4671DMX15TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, and sensing solutions for automotive, industrial, cloud, and consumer markets.
The NCP4671DMX15TCG belongs to onsemi's ultra-low-dropout linear regulator product line, engineered specifically for battery-powered portable electronics requiring sub-1 V input operation, high accuracy, and minimal quiescent power.
FAQ
What is the minimum input voltage required for NCP4671DMX15TCG to regulate 1.5 V output?
The NCP4671DMX15TCG requires VIN ≥ VOUT + 0.1 V = 1.6 V when VBIAS ≥ 3.1 V (VOUT + 1.6 V). Its ultra-low dropout architecture allows operation as low as 0.9 V input only when VBIAS is properly configured and load current is reduced; full 400 mA capability begins at 1.6 V VIN. Always verify against the dropout table in the datasheet for your specific VBIAS and temperature conditions.
Does NCP4671DMX15TCG include an integrated output discharge transistor?
Yes, the "D" suffix in NCP4671DMX15TCG denotes the auto-discharge version. It integrates an N-channel FET between VOUT and GND that activates automatically when CE is pulled low, discharging external output capacitance rapidly to prevent floating or unintended operation of downstream circuits during power-down sequences.
What is the recommended input capacitor configuration for NCP4671DMX15TCG?
Per the datasheet, use a 1 µF ceramic capacitor (C1) placed as close as possible to the VIN pin and GND, and a second 1 µF ceramic capacitor (C2) placed near the VBIAS pin and GND. These decoupling caps minimize impedance and improve line transient response; higher values or lower-ESR ceramics further enhance stability under dynamic load conditions.
Can NCP4671DMX15TCG operate with VBIAS lower than 3.1 V?
No - for the 1.5 V version (NCP4671DMX15TCG), VBIAS must be ≥ VOUT + 1.6 V = 3.1 V per datasheet specifications. Using VBIAS < 3.1 V risks improper biasing of the control circuitry, leading to regulation failure, increased dropout, or undefined behavior. Always maintain VBIAS within 3.1 V to 5.25 V for reliable operation.
How does the dual-rail architecture of NCP4671DMX15TCG improve PSRR performance?
The dual-rail architecture separates the LDO's control circuitry (powered by VBIAS) from the main power path (VIN), allowing independent optimization: VIN can carry switching noise from upstream DC/DC converters while VBIAS remains clean, resulting in 80 dB PSRR on VIN and 50 dB PSRR on VBIAS at 1 kHz - significantly higher than single-rail LDOs with comparable specs.
NCP4671DMX15TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.25V
- Voltage - Output (Min/Fixed):
- 1.5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.26V @ 400mA
- Current - Output:
- 400mA
- Current - Quiescent (Iq):
- 40 µA
- Current - Supply (Max):
- -
- PSRR:
- 80dB ~ 50dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XDFN (1.2x1.2)
NCP4671DMX15TCG FAQ
1.How can I place an order for NCP4671DMX15TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP4671DMX15TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP4671DMX15TCG reliable?
The price and inventory of NCP4671DMX15TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP4671DMX15TCG is usually 5 days.
3.What payment methods are accepted for NCP4671DMX15TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP4671DMX15TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP4671DMX15TCG?
NCP4671DMX15TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP4671DMX15TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP4671DMX15TCG?
For technical support, including NCP4671DMX15TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP4671DMX15TCG requirements.
6.How does Aetrix verify that NCP4671DMX15TCG is sourced from the original manufacturer or authorized distributors?
All NCP4671DMX15TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP4671DMX15TCG meets industry standards.
7.What is the process for return or replacement of NCP4671DMX15TCG?
All NCP4671DMX15TCG units undergo pre-shipment inspection (PSI). If there is an issue with NCP4671DMX15TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP4671DMX15TCG part is unused and in its original packaging.
Return procedure for NCP4671DMX15TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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