onsemi NCP585DSN125T1G
- Part No.:
- NCP585DSN125T1G
- Manufacturer:
- onsemi
- Package:
- SC-74A, SOT-753
- Datasheet:
-
NCP585DSN125T1G.pdf
- Description:
- IC REG LIN 1.25V 300MA SOT23-5
- Quantity:
- Payment:

- Shipping:

Inventory:2,452
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP585DSN125T1G from onsemi is a tri-mode 300 mA CMOS low-dropout (LDO) regulator with enable and auto-discharge functionality, designed for precision voltage regulation in portable battery-powered systems. It delivers a fixed 1.25 V output, supports input voltages up to 6.5 V, achieves 550 mV dropout at 300 mA (ECO = H), and operates across −40°C to +85°C ambient temperature - enabling use in handheld instrumentation and camcorders.
For engineers reviewing the NCP585DSN125T1G datasheet, pinout, applications, or equivalent options, key selection criteria include its tri-mode operation (CE/FT/LP), ultra-low quiescent current (3.5 µA in LP mode), ±2% output accuracy, 70 dB PSRR at 1 kHz, and SOT23−5 package compatibility with space-constrained PCB layouts.
Technical Context
The NCP585DSN125T1G implements a CMOS-based LDO architecture with three configurable operating modes controlled via the ECO pin: Chip Enable (CE), Fast Transient (FT), and Low Power (LP). Mode selection directly governs quiescent current (80 µA FT vs. 3.5 µA LP), load regulation (40 mV FT vs. 15 mV CE), and output accuracy (±3% LP vs. ±2% CE/FT).
Its internal circuitry includes fold-back current limiting, thermal shutdown protection, and an N-channel auto-discharge transistor (60 Ω typical RLow) activated when CE is deasserted. The device requires only 1.0 µF ceramic output capacitance and maintains stability across 0.1–100 µF ESR ranges in LP mode, while FT mode imposes tighter ESR constraints depending on load current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.25 V ±2% (CE/FT mode); ±3% in LP mode - ensures stable core logic or sensor biasing without external feedback. |
| Max Output Current | 300 mA continuous - sufficient for powering microcontrollers, RF transceivers, or analog front-ends in portable devices. |
| Dropout Voltage | Typ. 310 mV at 300 mA (VOUT = 1.25 V, ECO = H) - enables operation from single-cell Li-ion (3.0 V min) or two-cell alkaline (2.4 V min) sources. |
| Quiescent Current | 3.5 µA (LP mode, VOUT < 1.6 V); 80 µA (FT mode) - extends battery life in always-on monitoring or sleep-state applications. |
| PSRR | 70 dB at 1 kHz - suppresses switching noise from DC-DC converters feeding the LDO input, critical for ADC reference or audio signal chains. |
| Operating Temp | −40°C to +85°C ambient - validated for industrial-grade portable equipment deployed in variable environmental conditions. |
| Input Voltage Range | 1.4 V to 6.0 V - accommodates wide-input battery chemistries and intermediate rail generation in multi-rail systems. |
Pinout & Package
SOT23−5 package (Case 1212), 2.8 mm × 2.5 mm footprint, 1.0–1.3 mm height, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - Vin | Power supply input | Accepts 1.4–6.0 V input; requires 1.0 µF ceramic decoupling capacitor to GND for stability. |
| 2 - GND | Power ground reference | Common return path for input/output currents; must be low-impedance connection to PCB ground plane. |
| 3 - CE | Chip enable (active-high) | Drives regulator into shutdown (<0.1 µA ISD) when pulled low; threshold VTH,EN = 1.0 V (min). |
| 4 - ECO | Mode selection control | Connect to Vin for FT mode (fast transient response); connect to GND for LP mode (ultra-low Iq). |
| 5 - Vout | Regulated output | Delivers 1.25 V ±2%; requires 1.0 µF low-ESR ceramic capacitor placed adjacent to pin for transient stability. |
Key Features
| Feature | Design Value |
|---|---|
| Tri-mode operation | Hardware-selectable CE/FT/LP modes via ECO pin - enables dynamic trade-off between efficiency, speed, and noise performance. |
| Auto-discharge function | Integrated 60 Ω N-channel FET discharges Vout when CE is deasserted - prevents residual voltage from interfering with system power sequencing. |
| Ultra-low shutdown current | 0.1 µA max - eliminates battery drain during extended storage or deep-sleep states in IoT edge nodes. |
| High PSRR at 1 kHz | 70 dB - rejects ripple from upstream switchers, preserving signal integrity in mixed-signal SoC power domains. |
| Thermal & current protection | Fold-back current limit and thermal shutdown - prevents damage during output short-circuit or high-temperature operation. |
Applications
| Handheld Medical Instrumentation | Portable Audio DAC Power |
|---|---|
Use Scenario: Battery-powered blood glucose meters requiring stable 1.25 V reference for precision analog front-end (AFE) and microcontroller core logic. IC Role / Device Role / Timing Role: Primary voltage regulator supplying clean, low-noise 1.25 V to AFE and MCU VDD rails. Use Value: ±2% output accuracy and 70 dB PSRR ensure consistent ADC conversion results across battery discharge cycles and switching noise environments. |
Use Scenario: Compact Bluetooth headphones using a 1.25 V rail for stereo DAC and headphone amplifier biasing. IC Role / Device Role / Timing Role: Low-noise LDO delivering regulated 1.25 V to audio codec IC, minimizing audible hiss and distortion. Use Value: 3.5 µA quiescent current in LP mode extends playback time; fast transient response (FT mode) handles dynamic audio load spikes without droop. |
| Industrial Sensor Node MCU Core | Smart Camera Image Sensor Bias |
Use Scenario: LoRaWAN-enabled temperature/humidity sensor node powered by two AA cells (2.4–3.2 V range). IC Role / Device Role / Timing Role: Efficient step-down LDO generating 1.25 V for ARM Cortex-M0+ MCU core and radio transceiver logic. Use Value: 310 mV dropout enables >90% usable battery capacity; tri-mode operation allows firmware to optimize Iq during idle vs. active transmit phases. |
Use Scenario: Ultra-compact action camera requiring precise 1.25 V bias for CMOS image sensor analog block and PLL clock generation. IC Role / Device Role / Timing Role: Low-noise, high-PSRR regulator powering image sensor analog supply and timing circuitry. Use Value: 100 ppm/°C tempco and ±2% accuracy maintain consistent sensor gain and color fidelity across operating temperature range (−20°C to +60°C). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1700T-1202E/TT | Fixed 1.2 V output (not 1.25 V); 250 mA max; no tri-mode or ECO pin; 1.6 µA Iq (lower than NCP585DSN125T1G's LP mode). | Lacks auto-discharge and fast-transient capability; suitable only for static low-power loads without dynamic current demands. | Select when exact 1.25 V is non-critical and system-level power sequencing does not require Vout discharge. |
| Torex XC6206P122MR-G | Fixed 1.2 V output; 300 mA; no ECO pin; 1 µA Iq; 350 mV dropout at 300 mA - slightly higher dropout than NCP585DSN125T1G's 310 mV. | No mode selection or auto-discharge; simpler interface but less flexible for adaptive power management. | Choose for cost-sensitive designs where 1.2 V suffices and board space permits larger SOT-23-5 footprint compatibility. |
Compared with MCP1700T-1202E/TT and XC6206P122MR-G, the NCP585DSN125T1G uniquely provides 1.25 V precision, tri-mode adaptability, and integrated auto-discharge - making it optimal for portable systems requiring dynamic power state control and tight voltage tolerance.
Availability
NCP585DSN125T1G is available at Aetrix Electronics and suitable for handheld instrumentation, portable audio devices, and industrial sensor nodes requiring stable component supply, long-term lifecycle support, and Pb-free compliance.
Supply support for NCP585DSN125T1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, and sensing solutions for automotive, industrial, and portable electronics.
The NCP585 series belongs to onsemi's precision LDO portfolio, engineered specifically for battery-powered applications demanding ultra-low quiescent current, high PSRR, and flexible operational modes - addressing design challenges in wearables, medical devices, and IoT endpoints.
FAQ
What is the output voltage tolerance of the NCP585DSN125T1G under standard operating conditions?
The NCP585DSN125T1G provides a fixed 1.25 V output with ±2% tolerance over temperature (−40°C to +85°C), load (1 mA to 300 mA), and line (VIN = VOUT + 1.0 V) in CE and FT modes. In LP mode, tolerance widens to ±3%, reflecting the trade-off for ultra-low quiescent current. This specification is verified per the Electrical Characteristics table in the official datasheet (Rev. 14, page 3).
How does the ECO pin affect the performance of the NCP585DSN125T1G?
The ECO pin configures the NCP585DSN125T1G into either Fast Transient (FT) mode (ECO = VIN) or Low Power (LP) mode (ECO = GND). In FT mode, the device delivers 40 mV load regulation and 80 µA quiescent current; in LP mode, it achieves 3.5 µA Iq but relaxes load regulation to 15 mV and output accuracy to ±3%. This hardware-selectable dual-mode operation enables runtime optimization between responsiveness and battery life.
Does the NCP585DSN125T1G include built-in protection features?
Yes, the NCP585DSN125T1G integrates fold-back current limiting and thermal shutdown protection. When output current exceeds ~50 mA under short-circuit conditions, the device reduces output current to limit power dissipation. If junction temperature exceeds ~125°C, thermal shutdown disables the pass element until safe operating temperature is restored. These protections are inherent to the silicon design and require no external components.
What is the recommended output capacitor for stable operation of the NCP585DSN125T1G?
A 1.0 µF ceramic capacitor with low ESR is recommended for the NCP585DSN125T1G output. Per the Application Information section (page 10), this value ensures stability across all operating modes and load currents up to 300 mA. The capacitor must be placed physically close to the Vout and GND pins, with short, low-inductance traces - critical for maintaining phase margin during load transients.
Can the NCP585DSN125T1G be used with input voltages below 1.4 V?
No. The NCP585DSN125T1G has a minimum input voltage rating of 1.4 V, as specified in the Electrical Characteristics table (page 3). Operation below this voltage may result in improper regulation, failure to enable, or undefined behavior. For sub-1.4 V inputs, alternative regulators such as the NCP585DSN09T1G (0.9 V output) or dedicated ultra-low-VIN LDOs should be evaluated.
NCP585DSN125T1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.25V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.7V @ 300mA
- Current - Output:
- 300mA
- Current - Quiescent (Iq):
- 90 µA
- Current - Supply (Max):
- 111 µA
- PSRR:
- -
- Control Features:
- Enable
- Protection Features:
- Over Current
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-5
NCP585DSN125T1G FAQ
1.How can I place an order for NCP585DSN125T1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP585DSN125T1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP585DSN125T1G reliable?
The price and inventory of NCP585DSN125T1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP585DSN125T1G is usually 5 days.
3.What payment methods are accepted for NCP585DSN125T1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP585DSN125T1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP585DSN125T1G?
NCP585DSN125T1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP585DSN125T1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP585DSN125T1G?
For technical support, including NCP585DSN125T1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP585DSN125T1G requirements.
6.How does Aetrix verify that NCP585DSN125T1G is sourced from the original manufacturer or authorized distributors?
All NCP585DSN125T1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP585DSN125T1G meets industry standards.
7.What is the process for return or replacement of NCP585DSN125T1G?
All NCP585DSN125T1G units undergo pre-shipment inspection (PSI). If there is an issue with NCP585DSN125T1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP585DSN125T1G part is unused and in its original packaging.
Return procedure for NCP585DSN125T1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP585DSN125T1G Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

