onsemi NCP590MNDPTAG
- Part No.:
- NCP590MNDPTAG
- Manufacturer:
- onsemi
- Package:
- 8-VFDFN Exposed Pad
- Datasheet:
-
NCP590MNDPTAG.pdf
- Description:
- IC REG LINEAR 1.8V/2.8V 8DFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,256
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Product details
Overview
NCP590MNDPTAG from onsemi is a dual-output, ultra-low-dropout CMOS LDO voltage regulator in a 2×2 mm DFN8 package, delivering up to 300 mA per output at fixed 1.8 V and 2.8 V. It achieves ±0.9% output accuracy at 100 mA/25°C, features independent enable pins (EN1/EN2), and maintains stability with only 1.0 µF output capacitance. It is designed for power sequencing in portable microprocessor systems requiring tight voltage regulation and low quiescent current.
For engineers reviewing the NCP590MNDPTAG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail accuracy under 1.9% over temperature, dropout as low as 52 mV at 100 mA, independent enable control for rail sequencing, thermal shutdown protection, and compatibility with MLCC output capacitors without minimum load requirements.
Technical Context
The NCP590MNDPTAG integrates two fully independent LDO regulators sharing a common input (Vin) and ground (GND), each with dedicated error amplifiers, precision trimmed references, and PMOS pass transistors. Its architecture supports active output discharge during disable and includes input UVLO (1.9–2.1 V) and thermal shutdown (155°C).
Each regulator operates across an input range of 2.1 V to 5.5 V, delivers regulated outputs without minimum load, and sustains stability with output capacitors from 0.7 µF to 4.7 µF and any ESR-including zero-ESR MLCCs. The device uses internal compensation and requires no external components beyond input/output bypass capacitors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltages | 1.8 V (Vout1) and 2.8 V (Vout2); fixed, non-adjustable, factory-trimmed for precision sequencing |
| Max Output Current | 300 mA per channel; enables simultaneous powering of core and I/O rails in compact devices |
| Voltage Accuracy | ±0.9% at 100 mA/25°C; ensures reliable logic-level compliance for 1.8 V and 2.8 V interfaces |
| Dropout Voltage | 52 mV typical at 100 mA load; allows operation with minimal headroom-e.g., 2.8 V out from 2.85 V input |
| Quiescent Current | 80–125 µA (one regulator ON); extends battery life in always-on subsystems like real-time clocks or sensors |
| Enable Threshold | VIH = 0.95 V; supports direct interfacing with sub-1 V logic domains and low-voltage microcontrollers |
| PSRR @ 120 Hz | 55 dB (2.8 V output); suppresses ripple from noisy DC-DC converters feeding the LDO input |
Pinout & Package
Package: 2×2 mm DFN8 (Case 506AA), thermally enhanced with exposed GND pad. Requires soldering the thermal pad to PCB ground plane for optimal thermal performance (θJA = 158°C/W on 1 oz Cu, 207 mm²).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Vin) | Input supply | Bypass directly at IC with ≥1 µF ceramic capacitor; supports 2.1–5.5 V input range |
| 2 (EN1) | Enable for Vout1 | Logic-high >0.95 V activates 1.8 V regulator; compatible with 1.2 V and higher logic families |
| 3 (EN2) | Enable for Vout2 | Independent control of 2.8 V rail; enables flexible power-up/down sequencing |
| 4,5 (NC) | No-connect | Unbonded pins; must remain unconnected and unstubbed on PCB |
| 6 (GND) | Ground reference | Common return for both regulators; thermal pad must be connected to GND for thermal safety |
| 7 (Vout2) | 2.8 V regulated output | Delivers up to 300 mA; bypass with 0.7–4.7 µF capacitor (any ESR, including MLCC) |
| 8 (Vout1) | 1.8 V regulated output | Delivers up to 300 mA; stable with zero load and no minimum ESR requirement |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable inputs | EN1 and EN2 allow staggered startup/shutdown of 1.8 V and 2.8 V rails-critical for FPGA or ASIC power sequencing |
| Active output discharge | Internally pulls Vout1/Vout2 to GND when disabled, preventing floating outputs and ensuring fast, controlled rail collapse |
| No minimum load requirement | Regulators remain stable down to 0 mA load-enables use in standby modes where downstream circuitry is fully powered off |
| UVLO with hysteresis | Turns off both regulators below 1.9 V input and re-enables above 2.0 V, preventing brownout operation and erratic behavior |
| Thermal + current limiting | Shuts down at 155°C junction temperature and limits per-regulator current to ~750 mA-protects against short-circuit faults |
Applications
| Mobile Baseband Power | Digital Camera Core/I/O Rails |
|---|---|
|
Use Scenario: Dual-rail power for cellular baseband processors requiring 1.8 V core and 2.8 V analog/RF interface supplies. IC Role / Device Role / Timing Role: Primary LDO providing tightly regulated, sequenced, low-noise power to processor core and peripheral blocks. Use Value: Enables clean power delivery with <±0.9% accuracy and 52 mV dropout-maximizing battery runtime while meeting voltage tolerance specs for 28 nm/40 nm SoCs. |
Use Scenario: Independent voltage rails for image sensor digital core (1.8 V) and analog signal chain (2.8 V) in compact camera modules. IC Role / Device Role / Timing Role: Dual-output LDO managing rail separation and sequencing to prevent latch-up and ensure proper sensor initialization. Use Value: Eliminates need for two discrete LDOs-reducing BOM count, PCB area, and cost while maintaining <20 µVRMS noise on analog rail. |
| Portable Audio DSP Supply | PCMCIA Card Dual-Voltage Interface |
|
Use Scenario: Powering low-power audio DSPs with separate 1.8 V digital and 2.8 V ADC/DAC supplies in MP3 players or Bluetooth headsets. IC Role / Device Role / Timing Role: Precision dual-LDO delivering stable, low-noise bias to mixed-signal audio processing circuits. Use Value: PSRR of 55 dB at 120 Hz suppresses switching noise from upstream DC-DC converters-preserving SNR in audio signal paths. |
Use Scenario: Providing compliant 1.8 V and 2.8 V supplies to PCMCIA/CompactFlash cards operating in host devices with variable input voltage. IC Role / Device Role / Timing Role: Compact, thermally robust dual-LDO enabling hot-plug compatibility and rail isolation per PCMCIA spec. Use Value: 2×2 mm DFN8 footprint fits tight card-edge layouts; UVLO prevents partial powering during insertion/removal transients. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS70245PWPR | Fixed 1.8 V / 2.5 V outputs; higher quiescent current (125 µA typ. per rail); larger 5-mm × 6-mm TSSOP package | Requires PCB redesign for package size; lacks active discharge and sub-1 V enable threshold | Choose if 2.5 V rail is required instead of 2.8 V and board space permits larger footprint |
| MCP1826-1828ST-TR | Adjustable dual LDO (requires external resistors); ±2% accuracy; no independent enables; 3×3 mm SOT-23-8 package | Needs external feedback network; less accurate; unsuitable for strict sequencing or low-noise analog rails | Choose only for cost-sensitive designs where adjustable outputs and relaxed accuracy are acceptable |
Compared with TPS70245PWPR and MCP1826-1828ST-TR, the NCP590MNDPTAG uniquely combines fixed 1.8 V/2.8 V outputs, ±0.9% accuracy, independent enables, active discharge, and 2×2 mm DFN8 packaging-making it optimal for space-constrained, high-precision dual-rail portable systems.
Availability
NCP590MNDPTAG is available at Aetrix Electronics and suitable for mobile baseband power, portable audio DSP supply, digital camera core/I/O rails, and PCMCIA card dual-voltage interface applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for NCP590MNDPTAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor manufacturer specializing in energy-efficient power, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP590MNDPTAG belongs to onsemi's high-accuracy dual-LDO product line, engineered specifically for battery-powered portable electronics demanding precise, low-dropout, and space-efficient multi-rail regulation.
FAQ
What are the fixed output voltages of the NCP590MNDPTAG?
The NCP590MNDPTAG provides two fixed, factory-trimmed output voltages: 1.8 V on Pin 8 (Vout1) and 2.8 V on Pin 7 (Vout2). These values are specified in the official ordering information table and confirmed in the device marking code "DP" (1.8 V / 2.8 V). Neither output is adjustable-the NCP590MNDPTAG is a dedicated dual-fixed-voltage LDO.
Does the NCP590MNDPTAG require external compensation components?
No, the NCP590MNDPTAG is internally compensated and requires no external compensation network. Stability is guaranteed with output capacitors ranging from 0.7 µF to 4.7 µF and any ESR-including zero-ESR MLCCs-across the full operating temperature range. This eliminates design complexity and reduces BOM count compared to externally compensated LDOs.
Can the NCP590MNDPTAG operate with an input voltage lower than 2.1 V?
No-the NCP590MNDPTAG has a specified minimum input voltage of 2.1 V per its Recommended Operating Conditions. Below this, the internal UVLO circuit disables both regulators. The absolute maximum rating allows VIN down to –0.3 V, but functional operation is not guaranteed below 2.1 V, and the device will not regulate either 1.8 V or 2.8 V output.
How does the NCP590MNDPTAG handle thermal overload?
The NCP590MNDPTAG incorporates thermal shutdown protection that activates at approximately 155°C junction temperature (TjSD). When triggered, both regulators shut down completely until the die cools by ~15°C hysteresis. This protects the device and system during sustained overload or poor PCB thermal design, and recovery is automatic upon cooling-no reset signal required.
Is the exposed thermal pad on the NCP590MNDPTAG required to be connected to ground?
Yes-the exposed thermal pad (Pin 6 GND pad) must be soldered to a PCB ground plane for safe and reliable operation. Data sheet Figure 1 and the PIN FUNCTION table explicitly state: "The thermal pad should be connected to ground for best thermal performance." Leaving it unconnected degrades θJA by >100°C/W and risks thermal shutdown under moderate load.
NCP590MNDPTAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 8-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V, 2.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- -, 0.225V @ 300mA
- Current - Output:
- 300mA, 300mA
- Current - Quiescent (Iq):
- 125 µA
- Current - Supply (Max):
- 250 µA
- PSRR:
- 55dB (120Hz), 50dB ~ 40dB (120Hz ~ 1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN (2x2)
NCP590MNDPTAG FAQ
1.How can I place an order for NCP590MNDPTAG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP590MNDPTAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP590MNDPTAG reliable?
The price and inventory of NCP590MNDPTAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP590MNDPTAG is usually 5 days.
3.What payment methods are accepted for NCP590MNDPTAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP590MNDPTAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP590MNDPTAG?
NCP590MNDPTAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP590MNDPTAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP590MNDPTAG?
For technical support, including NCP590MNDPTAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP590MNDPTAG requirements.
6.How does Aetrix verify that NCP590MNDPTAG is sourced from the original manufacturer or authorized distributors?
All NCP590MNDPTAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP590MNDPTAG meets industry standards.
7.What is the process for return or replacement of NCP590MNDPTAG?
All NCP590MNDPTAG units undergo pre-shipment inspection (PSI). If there is an issue with NCP590MNDPTAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP590MNDPTAG part is unused and in its original packaging.
Return procedure for NCP590MNDPTAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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