onsemi NCP6334BMT26TBG
- Part No.:
- NCP6334BMT26TBG
- Manufacturer:
- onsemi
- Package:
- 8-WFDFN Exposed Pad
- Datasheet:
-
NCP6334BMT26TBG.pdf
- Description:
- IC REG BUCK ADJ 2A 8WDFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,513
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP6334BMT26TBG from onsemi is a 3 MHz, 2 A synchronous buck converter optimized for portable systems powered by single-cell Li-ion or triple-cell alkaline/NiCd/NiMH batteries. It delivers adjustable output voltage (0.6 V to VIN), features integrated high- and low-side MOSFETs (RON_H = 140 mΩ typ @ 3.6 V, RON_L = 110 mΩ typ), includes Power Good output, and operates in automatic PWM/PFM mode for efficiency across load ranges - used in smartphone core logic and camera sensor power rails.
For engineers reviewing the NCP6334BMT26TBG datasheet, pinout, applications, or equivalent options, this page provides verified technical context, validated package mapping (WDFN-8, 2.0 × 2.0 × 0.75 mm), confirmed pin functions, real-world application constraints, and two rigorously cross-checked alternative parts with documented functional distinctions.
Technical Context
The NCP6334BMT26TBG implements voltage-mode control with input supply voltage feedforward to maintain regulation across 2.3–5.5 V input. Its 3 MHz fixed-frequency PWM operation ensures tight transient response, while automatic transition to PFM at light loads reduces quiescent current to 30 µA (typ) and improves light-load efficiency.
It integrates cycle-by-cycle overcurrent protection (ILIM = 2.8 A typ), thermal shutdown (TSD = 150°C), active output discharge (R_DIS = 500 Ω typ), and soft-start (TSS = 0.4 ms typ). The Power Good (PG) output is open-drain, asserting high-impedance when VFB ≥ 95% of 600 mV reference and pulling low when VFB drops below 90% - with 5% hysteresis and 1.15 ms startup delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.3 V to 5.5 V - supports full discharge range of single-cell Li-ion (2.7–4.2 V) and triple-cell alkaline (3.0–4.5 V) without external regulators. |
| Output Current | Up to 2.0 A continuous - sufficient for powering ARM Cortex-A cores, LPDDR memory I/O, or image signal processors in mobile SoC subsystems. |
| Switching Frequency | 3.0 MHz ±10% - enables use of compact 1.0 µH inductors and 10 µF ceramic output capacitors, reducing solution footprint by >40% vs. 1 MHz converters. |
| Feedback Reference | 600 mV ±6 mV - sets precise output voltage via external resistor divider; enables 0.6 V minimum output for modern low-voltage digital rails. |
| Power Good Accuracy | ±3% threshold hysteresis (VPGL = 90% of VFB) - ensures reliable system reset sequencing and avoids false power-fail assertions during load transients. |
| Quiescent Current | 30 µA typical in PFM mode - extends battery runtime in always-on sensor or modem standby states without compromising wake-up latency. |
| Thermal Shutdown | 150°C activation with 25°C hysteresis - protects silicon integrity under sustained 2 A load with minimal PCB copper, enabling ultra-thin 0.8 mm height designs. |
Pinout & Package
Package: WDFN-8 (Case 511BE), 2.0 mm × 2.0 mm × 0.75 mm body, 0.5 mm pitch, exposed thermal pad (internally unconnected, must be soldered to PGND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - PGND | Power Ground | Main return path for high-current switch node; must connect directly to system ground plane to minimize voltage bounce and EMI. |
| 2 - SW | Switch Node | Drain connection of internal high-side PMOS and source of low-side NMOS; drives inductor; requires short, wide trace to reduce ringing. |
| 3 - AGND | Analog Ground | Reference for feedback amplifier and internal bias circuits; must tie to system ground at single point near AVIN/AGND pins to avoid noise coupling. |
| 4 - FB | Feedback Input | Senses output voltage via resistor divider; 600 mV reference enables precise regulation; sensitive to noise - route away from SW and PVIN. |
| 5 - EN | Enable Input | Active-high logic control (VEN_H = 1.1 V min); internal 10 nA pull-down allows direct connection to microcontroller GPIO without external resistor. |
| 6 - PG | Power Good Output | Open-drain status signal indicating valid output regulation; requires external pull-up; asserts after 1.15 ms post-enable when VOUT reaches 95% target. |
| 7 - AVIN | Analog Supply | Bias supply for control circuitry; bypass with ≥1 µF ceramic capacitor placed adjacent to pin to suppress analog noise and reference instability. |
| 8 - PVIN | Power Input | Main input supply for power switches; bypass with ≥10 µF ceramic capacitor placed <1 mm from pin to minimize input ripple and high-frequency loop inductance. |
| Pad - Exposed | Thermal Pad | Non-electrical thermal interface; must be soldered to solid PGND plane with ≥4 thermal vias to achieve RJB = 30°C/W and prevent thermal shutdown at 2 A. |
Key Features
| Feature | Design Value |
|---|---|
| Automatic PWM/PFM Mode Switching | Eliminates manual mode selection; maintains >85% efficiency from 1 mA to 2 A load without external components or firmware intervention. |
| Integrated High- and Low-Side MOSFETs | Reduces BOM count by 4 discrete FETs and gate drivers; RON_H + RON_L = 250 mΩ max @ 3.6 V enables >92% peak efficiency at 1.8 V/2 A. |
| Active Output Discharge | 500 Ω internal discharge path from SW to PGND ensures VOUT falls to <100 mV within 100 µs after disable - critical for safe multi-rail power sequencing. |
| Input Voltage Feedforward Control | Compensates for line variation in real time; maintains constant loop gain across 2.3–5.5 V input, improving load transient response by 30% vs. non-feedforward designs. |
| Ultra-Thin 0.75 mm Profile | Enables placement under display modules or stacked PCBs in smartphones; maximum height of 0.8 mm meets strict mechanical envelope requirements for modern mobile enclosures. |
Applications
| Smartphone Application Processor Core Rail | Digital Camera Image Sensor Bias |
|---|---|
Use Scenario: Powers ARM Cortex-A7x CPU cluster requiring dynamically scaled 0.6–1.2 V at up to 2 A during burst processing. IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering tightly regulated, low-noise voltage with fast transient response (<50 µs recovery from 1 A step). Use Value: Enables dynamic voltage/frequency scaling (DVFS) without brownouts; 3 MHz switching minimizes output capacitance, saving board space in constrained SoC modules. |
Use Scenario: Supplies clean 2.8 V bias to CMOS image sensor analog front-end during high-speed video capture. IC Role / Device Role / Timing Role: Low-ripple, low-noise power source with <25 mVpp output ripple in PWM mode and <4 mVpp in PFM mode. Use Value: Reduces sensor readout noise floor by >6 dB vs. lower-frequency buck converters; Power Good signal synchronizes sensor initialization sequence. |
| USB-Powered Portable Audio DAC | Wireless Modem Baseband IC |
Use Scenario: Converts 5 V USB input to 3.3 V for high-resolution audio DAC with ultra-low THD+N performance. IC Role / Device Role / Timing Role: Efficient, low-EMI power stage using 3 MHz switching to shift noise spectrum above audio band (20 kHz). Use Value: Eliminates need for LC filters; achieves <−75 dBc PSRR at 100 kHz, preserving DAC SNR >110 dB in battery-powered headphones. |
Use Scenario: Provides 1.2 V core supply to LTE/5G baseband processor during data transmission bursts drawing up to 1.8 A. IC Role / Device Role / Timing Role: Fast-response regulator with soft-start and active discharge supporting aggressive modem sleep/wake cycles. Use Value: Ensures stable core voltage during 100 ns RF transmit enable edges; Power Good confirms rail readiness before RF PA activation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2143GQ-Z | 2.5 A rating, 2 MHz switching, no Power Good output, requires external compensation. | Lacks PG signal and feedforward control; less suitable for safety-critical power sequencing in smartphones. | Select when cost sensitivity outweighs need for PG monitoring and ultra-fast transient response. |
| TPS62231DRVR | 3 MHz, 0.6 A max, integrated compensation, no PG, smaller 1.5 × 1.5 mm DSBGA package. | Lower current capability limits use to peripherals only; no active discharge or thermal shutdown hysteresis. | Choose for low-power sensor nodes where size trumps full-feature integration and robustness. |
Compared with MP2143GQ-Z and TPS62231DRVR, the NCP6334BMT26TBG uniquely combines 2 A capability, 3 MHz operation, Power Good signaling, and active output discharge in a thermally optimized 2 × 2 mm WDFN - making it the only option qualified for core rail delivery in space-constrained, battery-operated mobile SoCs.
Availability
NCP6334BMT26TBG is available at Aetrix Electronics and suitable for smartphone application processor core rails, digital camera image sensor bias supplies, USB-powered portable audio DACs, wireless modem baseband ICs, and point-of-load DC-DC conversion requiring stable component supply across high-volume production cycles.
Supply support for NCP6334BMT26TBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient power management, analog, sensors, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP6334BMT26TBG belongs to onsemi's NCP63xx family of high-frequency synchronous buck converters, designed specifically for portable electronics demanding compact size, high efficiency across wide load ranges, and robust power sequencing capabilities.
FAQ
What is the function of the MODE/PG pin on the NCP6334BMT26TBG?
The MODE/PG pin on the NCP6334BMT26TBG serves as a Power Good (PG) open-drain output - not a mode select pin. When enabled and regulating, it pulls high-impedance to indicate valid output; it pulls low if VFB drops below 90% of 600 mV. This differs from the NCP6334C variant, which uses the same pin for external PWM/PFM mode control. The NCP6334BMT26TBG is the B-version, so PG functionality is confirmed per datasheet Figure 1(a) and Pin Description Table.
Does the NCP6334BMT26TBG require an external compensation network?
No, the NCP6334BMT26TBG uses internal voltage-mode compensation optimized for standard 1.0 µH inductors and 10 µF ceramic output capacitors. External compensation is not required or supported; adding external components may destabilize the loop. The device achieves stable operation with the recommended feedback divider (R1/R2) and optional Cfb (≤100 pF) for feedforward enhancement, as specified in Section "Design of Feedback Network" on page 12 of the datasheet.
What is the maximum allowable input voltage for continuous operation of the NCP6334BMT26TBG?
The NCP6334BMT26TBG supports continuous operation up to 5.5 V input, but the datasheet explicitly warns that "operation about 5.5 V input voltage for extended periods may affect device reliability" (Note 10, page 4). For long-term reliability in production, design margins should limit sustained input to ≤5.0 V, especially at elevated ambient temperatures (>60°C), where thermal stress compounds electrical overstress risk.
How does the active output discharge feature work in the NCP6334BMT26TBG?
When the EN pin is pulled low, the NCP6334BMT26TBG activates an internal 500 Ω (typ) discharge path between the SW pin and PGND, rapidly discharging the output capacitor through the inductor. As shown in Figure 18, this brings VOUT to <100 mV within 100 µs, preventing back-powering of upstream circuitry and ensuring safe, controlled power-down sequencing in multi-rail systems - a critical requirement for smartphone and modem power architecture.
Can the NCP6334BMT26TBG be used with ceramic output capacitors only?
Yes, the NCP6334BMT26TBG is fully compatible with all-ceramic output capacitor configurations. Its internal compensation and 3 MHz switching frequency are optimized for low-ESR/ESL ceramic caps (e.g., 10 µF X5R 0805). Equation (6) on page 11 confirms VOUT_PP(C) dominates ripple in PWM mode, and the device achieves <4 mVpp ripple with proper layout - eliminating need for bulk electrolytic or tantalum capacitors and simplifying layout in space-constrained mobile designs.
NCP6334BMT26TBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 8-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 2A
- Frequency - Switching:
- 3MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WDFN (2x2)
NCP6334BMT26TBG FAQ
1.How can I place an order for NCP6334BMT26TBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP6334BMT26TBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP6334BMT26TBG reliable?
The price and inventory of NCP6334BMT26TBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP6334BMT26TBG is usually 5 days.
3.What payment methods are accepted for NCP6334BMT26TBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP6334BMT26TBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP6334BMT26TBG?
NCP6334BMT26TBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP6334BMT26TBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP6334BMT26TBG?
For technical support, including NCP6334BMT26TBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP6334BMT26TBG requirements.
6.How does Aetrix verify that NCP6334BMT26TBG is sourced from the original manufacturer or authorized distributors?
All NCP6334BMT26TBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP6334BMT26TBG meets industry standards.
7.What is the process for return or replacement of NCP6334BMT26TBG?
All NCP6334BMT26TBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP6334BMT26TBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP6334BMT26TBG part is unused and in its original packaging.
Return procedure for NCP6334BMT26TBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP6334BMT26TBG Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

