My Inquiry
My Account
onsemi NCP6914AFCAT1G
- Part No.:
- NCP6914AFCAT1G
- Manufacturer:
- onsemi
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 20-UFBGA, WLCSP
- Datasheet:
-
NCP6914AFCAT1G.pdf
- Description:
- IC REG 5OUT BCK/LNR 3MHZ 20WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,121
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP6914AFCAT1G from onsemi is a 5-channel power management IC integrating one 800 mA step-down DC-DC converter with Dynamic Voltage Scaling (DVS) and four 300 mA low-noise, low-dropout regulators (LDOs), all in a 1.77 × 2.06 mm WLCSP20 package. It delivers programmable output voltages (DC-DC: 0.6–3.3 V in 12.5 mV steps; LDOs: 1.0–3.3 V in 50 mV steps), supports I²C control at up to 3.4 MHz, and targets battery-powered portable subsystems including camera modules and application processors.
For engineers reviewing the NCP6914AFCAT1G datasheet, pinout, applications, or equivalent options, key selection considerations include its default power-up sequence (LDO1→LDO2→LDO3→DCDC), 72 µA quiescent current in active mode with all LDOs enabled, thermal warning/interrupt capability, and support for external clock synchronization up to 100 MHz via the SYNC pin.
Technical Context
The NCP6914AFCAT1G implements a synchronous buck converter operating at 3 MHz (±15%) with internal high-side and low-side MOSFETs (RONHS = 230 mΩ, RONLS = 200 mΩ), programmable soft-start (≤1 ms), and DVS ramp control (12.5 mV/1.33 s default). Its four LDOs feature independent input pins (VIN12, VIN3, VIN4), 50 µVrms typical output noise, and PSRR of −75 dB at 1 kHz.
Control is delivered via a 400 kHz / 3.4 MHz I²C interface with hardware enable (HWEN), open-drain power good (PG), interrupt (INTB), and external synchronization (SYNC) pins. The device includes under-voltage lockout (2.3 V threshold, 200 mV hysteresis), thermal shutdown (150 °C), and thermal warning (135 °C) with configurable rearm behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DC-DC Output Current | 800 mA maximum - sufficient to supply processor cores or high-current peripherals directly |
| LDO Output Current (each) | 300 mA - supports multiple low-power rails (e.g., sensors, memory, I/O) without external boost |
| DC-DC Switching Frequency | 3 MHz ±15% - enables use of compact 1.0 µH inductors and reduces EMI in space-constrained layouts |
| Quiescent Current (active) | 72 µA typical with DC-DC on and all LDOs enabled - extends battery life in always-on subsystems |
| Output Voltage Resolution | DC-DC: 12.5 mV steps; LDOs: 50 mV steps - enables precise rail tuning for voltage-sensitive logic and analog blocks |
| Thermal Protection | 150 °C shutdown with 35 °C hysteresis and 135 °C warning interrupt - prevents damage during sustained high-load operation |
| I²C Speed Support | Up to 3.4 MHz - allows fast register configuration and dynamic DVS updates without bus contention |
Pinout & Package
Package: 20-pin WLCSP (1.77 × 2.06 mm, 0.40 mm pitch), Case 567CV, Pb-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AVIN | Analog & digital supply input | Primary bias rail for internal circuitry; requires ≥1.0 µF ceramic bypass to AGND for stable reference and low-noise operation |
| PVIN1 | DC-DC power input | High-current input for buck stage; must be decoupled with 4.7 µF ceramic capacitor placed adjacent to pin |
| SW1 | DC-DC switch node | Connects to inductor; carries high di/dt switching current - requires tight layout and minimal trace inductance |
| VOUT1–VOUT4 | LDO regulated outputs | Each requires dedicated 2.2 µF ceramic output capacitor; independent enable/disable via I²C or sequencer |
| HWEN | Hardware enable input | Active-high pin with internal pull-down; initiates power-up sequence when asserted; disables all regulators when deasserted |
| PG | Open-drain power good output | AND-combines assigned channel PG signals; defaults to DC-DC only; configurable delay (0–512 ms) before assertion |
| INTB | Open-drain interrupt output | Signals thermal warning, clock validity (CLKOK), clock selection (CLKSEL), or overcurrent events; dual-edge sensitive |
| SYNC | External clock synchronization input | Accepts square/sine wave (2.55–100 MHz); enables deterministic switching frequency alignment across multiple PMICs |
Key Features
| Feature | Design Value |
|---|---|
| Customizable Power-Up Sequencer | Configurable 10-step sequence with per-rail delay (2–10 ms), voltage, and enable state - matches processor boot timing requirements |
| DVS Ramp Control | Programmable dV/dt (12.5 mV/1.33 s default) ensures glitch-free core voltage transitions during CPU frequency scaling |
| Active Output Discharge | Independent enable/disable per rail via DIS register - prevents floating outputs and unintended wake-up during sequencing |
| Low-Noise LDO Architecture | 50 µVrms output noise and −75 dB PSRR at 1 kHz - suitable for noise-sensitive analog circuits (e.g., camera ISP, ADCs) |
| Thermal Warning Interrupt | Asserts INTB at 135 °C - enables firmware to throttle loads or reduce DVS target before thermal shutdown at 150 °C |
Applications
| Smartphone Camera Module | Mobile Application Processor Core Rail |
|---|---|
Use Scenario: Powering image signal processor (ISP), CMOS sensor, and autofocus actuator in multi-camera smartphone designs. IC Role / Device Role / Timing Role: Supplies isolated, low-noise 2.8 V (LDO3/LDO4) for sensor analog front-end and 1.2 V (DC-DC) for ISP core with DVS support. Use Value: Independent LDO inputs allow connection to either battery or DC-DC output, enabling optimal efficiency and noise isolation per subsystem. |
Use Scenario: Delivering dynamically scaled voltage to ARM Cortex-A series application processors during DVFS transitions. IC Role / Device Role / Timing Role: DC-DC converter acts as primary core rail with programmable DVS ramp; LDOs supply I/O, memory, and peripheral rails. Use Value: 12.5 mV DVS step resolution and controlled ramp rate prevent system instability during voltage transitions under load. |
| Portable Media Player Audio Subsystem | GPS Receiver Baseband Power |
Use Scenario: Providing clean, regulated power to DACs, headphone amplifiers, and audio codecs in battery-operated media players. IC Role / Device Role / Timing Role: LDO1 and LDO2 deliver 1.8 V with <50 µVrms noise and −75 dB PSRR to analog audio paths. Use Value: Ultra-low noise and high PSRR suppress switching ripple from DC-DC stage, preserving SNR in audio signal chain. |
Use Scenario: Supplying precision 1.8 V and 2.8 V rails to GPS baseband IC and RF front-end in handheld navigation devices. IC Role / Device Role / Timing Role: LDOs power GPS baseband (1.8 V) and RF section (2.8 V); DC-DC supplies system logic from single-cell Li-Po. Use Value: 300 mA per LDO supports burst-mode GPS acquisition; thermal warning allows proactive throttling during extended hot-sky tracking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65136RGTR | 3-channel (1 buck + 2 LDOs); no DVS; 2.5 MHz switching; 600 mA DC-DC max | Lacks fourth LDO and programmable sequencing; lower integration for simpler subsystems | Choose when only three rails are needed and DVS is unnecessary - smaller footprint and lower cost |
| MAX20029ATPA/VY+ | 5-channel (1 buck + 4 LDOs); 2.2 MHz; 1 A DC-DC; integrated watchdog timer | Higher DC-DC current and automotive AEC-Q100 qualification; no thermal warning interrupt | Prefer for automotive infotainment where reliability certification and higher current headroom are required |
Compared with TPS65136RGTR and MAX20029ATPA/VY+, the NCP6914AFCAT1G uniquely combines fine-grained DVS control, thermal warning interrupt, and a 10-step customizable sequencer in a 1.77 × 2.06 mm WLCSP - making it optimal for space-constrained, thermally sensitive portable applications requiring precise rail coordination.
Availability
NCP6914AFCAT1G is available at Aetrix Electronics and suitable for smartphone camera modules, mobile application processor core rails, portable media player audio subsystems, and GPS receiver baseband power requiring stable component supply across high-mix production runs.
Supply support for NCP6914AFCAT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NCP6914AFCAT1G belongs to onsemi's mini PMIC family, designed specifically for battery-powered portable electronics requiring high integration, ultra-low quiescent current, and flexible power sequencing in sub-2 mm² footprints.
FAQ
What is the default power-up sequence for the NCP6914AFCAT1G?
The NCP6914AFCAT1G has a factory-programmed default sequence: LDO1 (1.20 V, enabled at 2 ms), LDO2 (1.80 V, 4 ms), LDO3 (2.80 V, 6 ms), LDO4 (2.80 V, disabled at 8 ms), and DC-DC (2.80 V, auto mode enabled at 10 ms). This sequence is defined in Table 6 of the datasheet and can be modified via I²C register writes before HWEN assertion.
Does the NCP6914AFCAT1G support Dynamic Voltage Scaling for its DC-DC converter?
Yes, the NCP6914AFCAT1G supports DVS on its DC-DC converter with programmable ramp rates (12.5 mV/1.33 s default) and two voltage registers (VPROGDCDC and VDVSDCDC). Voltage transitions are smooth and controlled via I²C commands, allowing real-time adaptation to processor load states without system disruption.
What is the purpose of the SYNC pin on the NCP6914AFCAT1G?
The SYNC pin on the NCP6914AFCAT1G accepts an external clock (2.55–100 MHz) to synchronize the DC-DC converter's switching frequency. When enabled, it eliminates beat frequencies between multiple PMICs and reduces EMI by aligning switching edges - critical in multi-rail, high-density portable PCBs.
How does thermal protection work in the NCP6914AFCAT1G?
The NCP6914AFCAT1G features dual thermal protection: a 135 °C warning that asserts INTB to notify firmware, and a 150 °C shutdown that disables all outputs. Hysteresis is 35 °C, so recovery occurs at 115 °C. Behavior after shutdown depends on REARM[1:0] bits - either factory defaults or pre-shutdown register values are restored.
Can the NCP6914AFCAT1G operate from a single-cell Li-Po battery?
Yes, the NCP6914AFCAT1G supports an input voltage range of 2.3 V to 5.5 V, fully covering the discharge curve of a single-cell Li-Po (typically 4.2 V down to ~2.7 V). Its UVLO threshold is 2.3 V with 200 mV hysteresis, ensuring reliable operation down to battery end-of-life while preventing erratic behavior during voltage sag.
NCP6914AFCAT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 20-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) (1), Linear (LDO) (4)
- Number of Outputs:
- 5
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 2.8V, 800mA
- Voltage/Current - Output 2:
- 1.2V, 300mA
- Voltage/Current - Output 3:
- 1.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-WLCSP (1.62x2.02)
NCP6914AFCAT1G FAQ
1.How can I place an order for NCP6914AFCAT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP6914AFCAT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP6914AFCAT1G reliable?
The price and inventory of NCP6914AFCAT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP6914AFCAT1G is usually 5 days.
3.What payment methods are accepted for NCP6914AFCAT1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP6914AFCAT1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP6914AFCAT1G?
NCP6914AFCAT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP6914AFCAT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP6914AFCAT1G?
For technical support, including NCP6914AFCAT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP6914AFCAT1G requirements.
6.How does Aetrix verify that NCP6914AFCAT1G is sourced from the original manufacturer or authorized distributors?
All NCP6914AFCAT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP6914AFCAT1G meets industry standards.
7.What is the process for return or replacement of NCP6914AFCAT1G?
All NCP6914AFCAT1G units undergo pre-shipment inspection (PSI). If there is an issue with NCP6914AFCAT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP6914AFCAT1G part is unused and in its original packaging.
Return procedure for NCP6914AFCAT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP6914AFCAT1G Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
