onsemi NCP6914AFCDT1G
- Part No.:
- NCP6914AFCDT1G
- Manufacturer:
- onsemi
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- -
- Datasheet:
-
NCP6914AFCDT1G.pdf
- Description:
- IC REG 5OUT BCK/LNR 3MHZ 20WLCSP
- Quantity:
- Payment:

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Inventory:1,108
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Product details
Overview
NCP6914AFCDT1G from onsemi is a 5-channel PMIC integrating one 800 mA step-down DC-DC converter with Dynamic Voltage Scaling (DVS) and four 300 mA low-noise LDOs in a 1.77 × 2.06 mm WLCSP20 package. It delivers programmable output voltages (DCDC: 0.6–3.3 V in 12.5 mV steps; LDOs: 1.0–3.3 V in 50 mV steps), supports I²C control at up to 3.4 MHz, and features hardware enable, power good, interrupt, and external synchronization pins. It is designed for battery-powered portable subsystems including camera modules and application processors.
For engineers reviewing the NCP6914AFCDT1G datasheet, pinout, applications, or equivalent options, key selection considerations include its default power-up sequence (DCDC→LDO1→LDO2→LDO3→LDO4), 72 µA quiescent current in full operation, 50 µVrms LDO output noise, thermal warning/interrupt capability, and support for external clock synchronization at 2.55–100 MHz.
Technical Context
The NCP6914AFCDT1G implements a synchronous buck converter operating at 3 MHz (±15%) with integrated high-side and low-side MOSFETs (RONHS = 230 mΩ, RONLS = 200 mΩ), soft-start (≤1 ms), and active output discharge. Its four LDOs feature independent input pins (VIN12, VIN3, VIN4), dropout voltages as low as 90 mV (LDO3/4 @ 300 mA), and PSRR of −75 dB at 1 kHz.
Control is implemented via a 400 kHz / 3.4 MHz I²C interface with register-programmable DVS ramp timing (1.33–10.67 µs per 12.5 mV step), customizable power-up sequencing (default: 2–10 ms staggered enables), and dual-mode operation (PWM/automatic PFM). Thermal protection includes 135°C warning interrupt and 150°C shutdown with hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DCDC Output Current | 800 mA max - sufficient to power application processor cores or high-speed interfaces |
| LDO Output Current | 300 mA per channel - supports multiple peripheral rails (e.g., sensor, memory, audio) |
| DCDC Switching Frequency | 2.7–3.3 MHz - enables use of compact 1.0 µH inductor and 10 µF output capacitor |
| LDO Output Noise | 50 µVrms - meets low-noise requirements for RF, camera, and precision analog circuits |
| Quiescent Current | 72 µA (all LDOs on, DCDC active, no load) - extends battery life in always-on subsystems |
| I²C Speed Support | Up to 3.4 MHz - enables fast register configuration during boot or dynamic voltage scaling |
| Input Voltage Range | 2.3–5.5 V - compatible with single-cell Li-Po (3.0–4.2 V) and triple-alkaline (4.5 V) supplies |
Pinout & Package
Package: 20-pin WLCSP (1.77 × 2.06 mm, 0.40 mm pitch, Case 567CV), Pb-free, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AVIN | Analog & digital supply input | Primary bias rail for internal circuitry; requires ≥1.0 µF ceramic bypass to AGND |
| PVIN1 | DCDC power input | High-current input for buck converter; requires 4.7 µF ceramic decoupling |
| SW1 | DCDC switch node | Connects to inductor; carries high di/dt switching current; layout critical for EMI |
| FB1 | DCDC feedback input | Resistor-divider connection point for precise output voltage regulation |
| VIN12, VIN3, VIN4 | LDO input supplies | Independent inputs allow flexible rail sourcing (e.g., LDO1/2 from DCDC, LDO3/4 from battery) |
| VOUT1–VOUT4 | LDO regulated outputs | Each requires 2.2 µF ceramic output capacitor; supports 1.0–3.3 V programmable outputs |
| HWEN | Hardware enable input | Active-high logic input with internal pull-down; initiates default power-up sequence when asserted |
| PG, INTB | Open-drain status outputs | PG indicates combined power-good status; INTB signals thermal warning, clock faults, or overcurrent |
| SCL/SDA | I²C interface | Supports standard/fast-mode plus high-speed (3.4 MHz); bidirectional data and clock lines |
| SYNC | External clock input | Accepts 2.55–100 MHz square/sine wave; enables synchronized switching to reduce EMI |
Key Features
| Feature | Design Value |
|---|---|
| Customizable Power-Up Sequence | Factory-programmed 2–10 ms staggered enable order (DCDC → LDO1 → LDO2 → LDO3 → LDO4) prevents inrush current overload |
| DVS with Controlled dV/dt | Programmable 12.5 mV/step ramp timing (1.33–10.67 µs/step) avoids processor brownout during voltage transitions |
| Thermal Warning Interrupt | 135°C threshold triggers INTB before shutdown, enabling firmware-driven thermal mitigation (e.g., clock throttling) |
| Active Output Discharge | Configurable per-rail discharge ensures clean power-down sequencing and prevents floating nodes |
| Low-Noise LDO Architecture | 50 µVrms noise + −75 dB PSRR at 1 kHz enables direct powering of image sensors and RF front-ends |
Applications
| Mobile Camera Module | Application Processor Core Supply |
|---|---|
|
Use Scenario: Dual-camera system in smartphone requiring independent, low-noise, sequenced power rails for ISP, sensor, and flash IC. IC Role / Device Role / Timing Role: NCP6914AFCDT1G provides DCDC for core voltage (1.2 V), LDO1/LDO2 for sensor analog/digital (1.8 V), LDO3/LDO4 for flash driver (2.8 V), with 2–10 ms power-up delay alignment. Use Value: 50 µVrms LDO noise prevents image banding; DVS enables dynamic core voltage scaling during video capture vs. idle. |
Use Scenario: Low-power application processor (e.g., ARM Cortex-A series) in portable media player requiring adaptive core voltage and clean I/O rails. IC Role / Device Role / Timing Role: NCP6914AFCDT1G delivers 800 mA DCDC output (1.2 V) with DVS, while LDOs supply 1.8 V I/O and 2.8 V memory interface with independent enable control. Use Value: 95% peak DCDC efficiency and 72 µA quiescent current extend battery runtime; I²C programmability allows runtime voltage adjustment based on workload. |
| GPS Receiver Front-End | Portable Medical Sensor Hub |
|
Use Scenario: GNSS receiver module needing ultra-low-noise 1.8 V LDO supply for RF frontend and 2.8 V for baseband ASIC. IC Role / Device Role / Timing Role: NCP6914AFCDT1G uses LDO1 (1.8 V) and LDO3 (2.8 V) with dedicated input pins and 2.2 µF output caps to isolate noise-sensitive analog sections. Use Value: −75 dB PSRR at 1 kHz and 50 µVrms noise ensure minimal phase noise degradation in GPS signal acquisition. |
Use Scenario: Wearable ECG/PPG sensor hub requiring reliable, low-quiescent, multi-rail power for analog front-end, MCU, and BLE radio. IC Role / Device Role / Timing Role: NCP6914AFCDT1G powers MCU core (DCDC, 1.2 V), analog sensor bias (LDO1, 1.8 V), digital logic (LDO2, 1.8 V), and BLE transceiver (LDO4, 2.8 V) with thermal warning for safety-critical operation. Use Value: 150°C thermal shutdown and 135°C interrupt prevent overheating in sealed enclosures; <2 µA off-mode current preserves battery during standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | 3 DCDC + 2 LDOs; 2.7–5.5 V input; no DVS; larger 4×4 mm QFN package | Lacks dynamic voltage scaling and thermal warning interrupt; higher quiescent current (100 µA) | Choose when fixed-voltage rails and cost-sensitive QFN assembly are prioritized over DVS and ultra-low noise |
| RTQ2134B-WE | 1 DCDC + 3 LDOs; 2.5–5.5 V input; 3 MHz switching; 40 µVrms LDO noise; WLCSP20 package | One fewer LDO channel; no external SYNC pin or thermal warning interrupt; lower max DCDC current (600 mA) | Choose when footprint and noise are critical but 4 LDOs and thermal monitoring are not required |
Compared with TPS65023RSBR and RTQ2134B-WE, the NCP6914AFCDT1G uniquely combines DVS, thermal warning interrupt, and 4 independent LDOs in a 1.77 × 2.06 mm WLCSP-enabling compact, thermally aware, dynamically scalable power for advanced portable SoCs.
Availability
NCP6914AFCDT1G is available at Aetrix Electronics and suitable for mobile camera modules, application processor core supplies, GPS receivers, and portable medical sensor hubs requiring stable component supply across design-in, prototyping, and volume production phases.
Supply support for NCP6914AFCDT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Nasdaq: ON) is a global semiconductor leader delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NCP6914AFCDT1G belongs to onsemi's mini-PMIC family, engineered specifically for space-constrained, battery-powered portable subsystems-emphasizing ultra-low quiescent current, programmable sequencing, and integration of DCDC+LDO functionality in wafer-level chip-scale packaging.
FAQ
What is the default power-up sequence of the NCP6914AFCDT1G?
The NCP6914AFCDT1G has a factory-programmed default power-up sequence: DCDC enables at t=2 ms (1.20 V), followed by LDO1 at t=4 ms (1.80 V), LDO2 at t=6 ms (1.80 V), LDO3 at t=8 ms (2.80 V), and LDO4 at t=10 ms (2.80 V). This staggered enable minimizes inrush current and ensures proper subsystem initialization. The sequence can be reprogrammed via I²C registers or ordered with alternate configurations (e.g., NCP6914AFCAT1G).
Does the NCP6914AFCDT1G support Dynamic Voltage Scaling (DVS) on its DCDC converter?
Yes, the NCP6914AFCDT1G supports DVS on its DCDC converter with programmable 12.5 mV output steps and configurable ramp timing (1.33–10.67 µs per step). DVS is implemented using two voltage registers (VPROGDCDC and VDVSDCDC) and a GO bit to select between them. This enables smooth, controlled voltage transitions-critical for application processor performance scaling without brownout-while maintaining regulation integrity throughout the ramp.
What thermal protection features does the NCP6914AFCDT1G provide?
The NCP6914AFCDT1G includes both thermal warning and shutdown protection: a 135°C warning threshold triggers the INTB interrupt to alert the host processor, and a 150°C shutdown threshold disables all outputs to prevent damage. Hysteresis is 35°C, ensuring stable recovery. These functions activate only during active operation (at least one regulator enabled) and are configurable via I²C registers-enabling firmware-driven thermal management in portable devices.
Can the NCP6914AFCDT1G synchronize its DCDC switching frequency to an external clock?
Yes, the NCP6914AFCDT1G accepts an external clock on the SYNC pin (2.55–100 MHz square or sine wave) and divides it via a 5-bit SYNCRATIO register to match its internal 3 MHz ±15% target. With SYNCAUTO=1, it automatically switches between internal and external clocks based on validity. This reduces EMI by aligning switching edges with system clocks-particularly valuable in noise-sensitive RF and imaging applications where the NCP6914AFCDT1G is deployed.
What is the output noise performance of the LDOs in the NCP6914AFCDT1G?
The LDOs in the NCP6914AFCDT1G deliver 50 µVrms typical output noise (10 Hz–100 kHz, 150 mA load) and −75 dB PSRR at 1 kHz. This low-noise performance is achieved through optimized internal compensation and independent input pins (VIN12/VIN3/VIN4), allowing placement of local bulk capacitance. It directly supports noise-sensitive analog blocks such as camera image sensors, GPS RF front-ends, and precision medical sensor signal chains powered by the NCP6914AFCDT1G.
NCP6914AFCDT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- -
- Number of Outputs:
- -
- Frequency - Switching:
- -
- Voltage/Current - Output 1:
- -
- Voltage/Current - Output 2:
- -
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- -
- w/Supervisor:
- -
- w/Sequencer:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
NCP6914AFCDT1G FAQ
1.How can I place an order for NCP6914AFCDT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP6914AFCDT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP6914AFCDT1G reliable?
The price and inventory of NCP6914AFCDT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP6914AFCDT1G is usually 5 days.
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Once your NCP6914AFCDT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP6914AFCDT1G?
For technical support, including NCP6914AFCDT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP6914AFCDT1G requirements.
6.How does Aetrix verify that NCP6914AFCDT1G is sourced from the original manufacturer or authorized distributors?
All NCP6914AFCDT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP6914AFCDT1G meets industry standards.
7.What is the process for return or replacement of NCP6914AFCDT1G?
All NCP6914AFCDT1G units undergo pre-shipment inspection (PSI). If there is an issue with NCP6914AFCDT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP6914AFCDT1G part is unused and in its original packaging.
Return procedure for NCP6914AFCDT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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