onsemi NCP692MN15T2G
- Part No.:
- NCP692MN15T2G
- Manufacturer:
- onsemi
- Package:
- 6-VDFN Exposed Pad
- Datasheet:
-
NCP692MN15T2G.pdf
- Description:
- IC REG LINEAR 1.5V 1A 6DFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
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Product details
Overview
NCP692MN15T2G from onsemi is a 1.5 V fixed-output, 1 A low-dropout (LDO) voltage regulator in a 6-lead DFN3x3 package, featuring active-high enable, ±2% output voltage tolerance over −40°C to 125°C, 190 mV dropout at 1 A (VOUT = 2.5 V), and 50 µVRMS output noise. It delivers stable power for FPGA core rails and portable battery-powered systems requiring low quiescent current and high PSRR.
For engineers reviewing the NCP692MN15T2G datasheet, pinout, applications, or equivalent options, key selection criteria include enable polarity (active-high), thermal shutdown at 175°C, compatibility with low-ESR ceramic capacitors, and support for space-constrained PCB layouts with exposed thermal pad.
Technical Context
The NCP692MN15T2G implements a CMOS-based LDO architecture with integrated bandgap reference, MOSFET driver, current limiting, thermal shutdown, and active output discharge. Its fixed 1.5 V output is internally trimmed and does not require external feedback resistors.
It uses a dedicated SNS (sense) pin for remote output voltage sensing-critical for maintaining regulation accuracy under PCB trace resistance-and features an EN pin that asserts high to activate regulation, enabling precise power sequencing in multi-rail systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.5 V ±2% over −40°C to 125°C - ensures stable core supply for 1.5 V logic domains without external resistor network. |
| Max Output Current | 1 A continuous - supports FPGA I/O banks, DSP cores, and microprocessor subsystems with peak transient loads. |
| Dropout Voltage | 190 mV at 1 A (VOUT = 2.5 V); 290 mV at 1 A (VOUT = 1.5 V) - enables operation from 1.79 V input, preserving headroom in single-cell Li-ion or 2-cell alkaline systems. |
| Ground Current | 145 µA typical at 1 A load - minimizes system standby power loss in always-on portable applications. |
| PSRR | 62 dB at 120 Hz, 55 dB at 1 kHz - suppresses ripple from switching pre-regulators feeding the LDO input. |
| Output Noise | 50 µVRMS (200 Hz–100 kHz) - meets low-noise requirements for ADC reference supplies and RF bias rails. |
| Enable Threshold | VEN_Hi = 0.9 V min, VEN_Lo = 0.4 V max - compatible with 1.8 V and 3.3 V GPIOs for clean digital control without level-shifting. |
Pinout & Package
Package: DFN6 3×3 mm, 0.95 mm pitch, exposed thermal pad (Case 506AH, MN suffix). Thermal pad must be soldered to PCB copper for effective heat dissipation (RJA = 70°C/W with 645 mm² Cu).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 6 | IN | Primary input voltage supply pins - both must be connected in parallel to deliver full 1 A output current and minimize IR drop. |
| 2 | GND | Power ground tied to die via lead frame - requires direct connection to large PCB copper pour for thermal and EMI performance. |
| 3 | EN | Active-high enable input - drives internal regulator ON when ≥0.9 V; pulls output to GND when disabled (with active discharge). |
| 4 | OUT | Regulated 1.5 V output - connects directly to load and local decoupling capacitor (≥1 µF ceramic recommended). |
| 5 | SNS | Sense input - must be routed separately from OUT to load point to compensate for PCB trace resistance and maintain tight regulation. |
Key Features
| Feature | Design Value |
|---|---|
| Active-high enable logic | Eliminates need for external inverters in systems using 3.3 V/1.8 V microcontroller GPIOs for power sequencing. |
| Remote sense (SNS) pin | Compensates for up to 100 mΩ of PCB trace resistance between regulator and load, maintaining ±2% regulation at point-of-load. |
| Active output discharge | Forces regulated output to GND within microseconds after disable, preventing floating voltages during power-down sequences. |
| Thermal shutdown with hysteresis | Shuts down at 175°C and re-enables only after cooling by ≥10°C - prevents thermal cycling damage during sustained overload. |
| Enhanced ESD protection | 4 kV HBM / 200 V MM rating - reduces risk of field failure in handling and assembly of portable electronics. |
Applications
| Laptop Core Power | FPGA I/O Bank Supply |
|---|---|
Use Scenario: Providing clean 1.5 V supply to DDR memory interfaces and configurable logic blocks in ultra-thin notebooks. IC Role / Device Role / Timing Role: Primary post-regulator delivering low-noise, tightly regulated voltage to sensitive FPGA I/O banks with dynamic current demands up to 1 A. Use Value: Maintains signal integrity with 50 µVRMS noise and fast load transient response (<50 µs recovery), reducing bit error rates in high-speed memory links. | Use Scenario: Powering 1.5 V I/O standards (e.g., SSTL_15, HSTL_I) on Xilinx Artix-7 or Intel MAX 10 FPGA development boards. IC Role / Device Role / Timing Role: Fixed-output LDO supplying stable voltage to FPGA I/O banks while supporting independent enable control per bank. Use Value: Active-high EN allows synchronized power-up with configuration logic; SNS pin ensures <±2% regulation at connector pins despite board-level IR drop. |
| Portable Medical Sensor Hub | Industrial PLC Digital I/O Module |
Use Scenario: Regulating battery-derived input to power analog front-end ICs and low-power MCU cores in handheld ECG monitors. IC Role / Device Role / Timing Role: Low-quiescent-current LDO enabling >100-hour battery life while delivering 1.5 V to precision ADC reference circuits. Use Value: 145 µA ground current at full load and 50 µVRMS noise preserve SNR in sub-µV biomedical signal chains. | Use Scenario: Supplying isolated 1.5 V logic rails for optocoupler drivers and digital isolators in DIN-rail mounted programmable logic controllers. IC Role / Device Role / Timing Role: Industrial-grade LDO with AEC-Q100-aligned robustness (NCV variant available), operating from 1.79–6.0 V input across wide temperature range. Use Value: −40°C to 125°C operating range and thermal shutdown ensure reliability in uncooled enclosures; 4 kV ESD withstand protects against factory ESD events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NCP691MN15T2G | Same 1.5 V fixed output, but EN pin is active-low - requires inverted control signal or external inverter. | Suitable where host controller provides active-low enable (e.g., legacy microcontrollers with open-drain reset outputs). | Select when system-level enable logic is n-active; otherwise NCP692MN15T2G simplifies interface design. |
| TPS7A2015PDQNR | 1.5 V fixed, 1 A, but lower ground current (6.5 µA typ at no load) and higher PSRR (75 dB @ 1 kHz); no SNS pin. | Better suited for ultra-low-power always-on sensors; lacks remote sensing for point-of-load accuracy. | Choose for battery lifetime-critical applications without long trace runs; retain NCP692MN15T2G when SNS compensation is required. |
Compared with NCP691MN15T2G, the NCP692MN15T2G eliminates external level-shifting for enable control; compared with TPS7A2015PDQNR, it trades ultra-low quiescent current for remote sensing capability critical in high-accuracy power delivery.
Availability
NCP692MN15T2G is available at Aetrix Electronics and suitable for laptop power management, FPGA I/O rail regulation, and portable medical sensor hubs requiring stable component supply, automotive-qualified alternatives (NCV8690 variants), and long-term production continuity.
Supply support for NCP692MN15T2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient power management, analog, sensor, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The NCP692MN15T2G belongs to the NCP69x CMOS LDO family, designed specifically for space-constrained, battery-powered applications demanding high PSRR, low noise, and robust thermal protection in compact DFN packages.
FAQ
What is the minimum input voltage required for NCP692MN15T2G to deliver 1 A at 1.5 V output?
The minimum input voltage is determined by dropout: VIN(min) = VOUT + VDO. Per datasheet Table 6, VDO = 290 mV at 1 A for 1.5 V output, so VIN(min) = 1.79 V. The device specifies 1.5 V as absolute minimum VIN, but 1.79 V is required for guaranteed 1 A operation. NCP692MN15T2G must be supplied ≥1.79 V to maintain regulation under full load.
Does NCP692MN15T2G require an external bypass capacitor on the SNS pin?
No, the SNS pin of NCP692MN15T2G is not bypassed externally. It must be connected directly to the OUT pin (for fixed versions) or to the feedback divider node (for adjustable versions) using a short, low-impedance trace. Adding capacitance to SNS would destabilize the control loop and is explicitly prohibited in the datasheet's Applications Information section.
Can NCP692MN15T2G be used without connecting the EN pin?
Yes, but only if the system requires the regulator to be always enabled. Leaving EN unconnected risks undefined behavior due to floating input. The datasheet recommends tying EN to VIN if enable functionality is unused. For NCP692MN15T2G, this ensures reliable turn-on whenever input power is present and avoids potential oscillation or partial enable states.
What is the thermal performance of NCP692MN15T2G on a standard 1 oz FR4 PCB?
On a standard 1 oz FR4 board with 64 mm² copper area, NCP692MN15T2G has RJA = 169°C/W (Table 4). At 1 A load with 1.79 V input and 1.5 V output, power dissipation is ~290 mW. Junction temperature rise is then ΔT = 0.29 W × 169°C/W ≈ 49°C. With 25°C ambient, TJ ≈ 74°C - well below the 125°C max operating limit, confirming safe operation without heatsinking.
Is NCP692MN15T2G pin-compatible with other devices in the NCP69x family?
Yes, all NCP690/NCP691/NCP692/NCV8690 devices share identical DFN6 3×3 mm package and pinout (IN, EN/SNS/N/C, OUT, SNS/ADJ, GND). However, pin function differs: NCP690 uses Pin 3 as N/C; NCP691 uses Pin 3 as active-low EN; NCP692 uses Pin 3 as active-high EN. So while physically pin-compatible, electrical behavior of Pin 3 must be verified per variant. NCP692MN15T2G requires high-enable logic.
NCP692MN15T2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-VDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.41V @ 1A
- Current - Output:
- 1A
- Current - Quiescent (Iq):
- 200 µA
- Current - Supply (Max):
- 240 µA
- PSRR:
- -
- Control Features:
- Enable
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-DFN (3x3)
NCP692MN15T2G FAQ
1.How can I place an order for NCP692MN15T2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP692MN15T2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP692MN15T2G reliable?
The price and inventory of NCP692MN15T2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP692MN15T2G is usually 5 days.
3.What payment methods are accepted for NCP692MN15T2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP692MN15T2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP692MN15T2G?
NCP692MN15T2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP692MN15T2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP692MN15T2G?
For technical support, including NCP692MN15T2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP692MN15T2G requirements.
6.How does Aetrix verify that NCP692MN15T2G is sourced from the original manufacturer or authorized distributors?
All NCP692MN15T2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP692MN15T2G meets industry standards.
7.What is the process for return or replacement of NCP692MN15T2G?
All NCP692MN15T2G units undergo pre-shipment inspection (PSI). If there is an issue with NCP692MN15T2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP692MN15T2G part is unused and in its original packaging.
Return procedure for NCP692MN15T2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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