onsemi NCP720BMT105TBG
- Part No.:
- NCP720BMT105TBG
- Manufacturer:
- onsemi
- Package:
- 6-WDFN Exposed Pad
- Datasheet:
-
NCP720BMT105TBG.pdf
- Description:
- IC REG LINEAR 1.05V 350MA 6WDFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,711
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Product details
Overview
NCP720BMT105TBG from onsemi is a 350 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering fixed 1.05 V output with ±2% accuracy over −40°C to +125°C, ultra-low 110 mV typical dropout at full load, and stable operation with 2.2 µF ceramic output capacitor - designed for noise-sensitive, space-constrained portable electronics including smartphones and camera modules.
For engineers reviewing the NCP720BMT105TBG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail bias architecture, VBIAS-dependent dropout behavior, EN-controlled shutdown with 0.5 µA typical quiescent current in disable mode, and WDFN6 thermal performance under high ambient conditions.
Technical Context
The NCP720BMT105TBG implements a dual-input VLDO architecture: VIN supplies the NMOS pass element while VBIAS powers internal control circuitry, enabling independent optimization of power path and bias rail. This decoupling allows stable regulation even when VIN approaches VOUT, with VBIAS maintaining >2.4 V for proper UVLO and reference operation.
Its built-in soft-start ensures monotonic VOUT rise to limit inrush current, and thermal shutdown activates at +160°C with hysteresis reset at +140°C. The device achieves high PSRR (>65 dB at 1 kHz for VBIAS) and low output noise (40 µVRMS, 10 Hz–100 kHz), critical for powering RF and analog subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.05 V - factory-programmed; enables precise core I/O rail generation without external feedback. |
| VIN Range | 0.8 V to 5.5 V - supports direct battery input down to single-cell Li-ion or NiMH discharge endpoints. |
| VBIAS Range | 2.4 V to 5.5 V - must exceed VOUT + 1.4 V (≥2.45 V) for guaranteed regulation and UVLO release. |
| VIN Dropout | 110 mV typ. at 350 mA - permits operation with minimal headroom, e.g., 1.16 V input for 1.05 V output. |
| Quiescent Current (IQ) | 80 µA typ. at full load - minimizes standby power loss in always-on subsystems. |
| Shutdown Current | 0.5 µA typ. - reduces system-level leakage during deep sleep modes. |
| PSRR @ 1 kHz | 65 dB (VBIAS), 65 dB (VIN) - suppresses switching noise from upstream DC/DC converters. |
| Stability | Guaranteed with 2.2 µF ceramic output capacitor - eliminates need for large tantalum or electrolytic caps. |
Pinout & Package
Package: WDFN6 2 mm × 2 mm, 0.65 mm pitch, exposed thermal pad (Case 511BR). Soldering the thermal pad to PCB ground plane is required for RJA = 65°C/W performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output node | Delivers stable 1.05 V; connects directly to load with minimal trace inductance. |
| 2 - N/C | No internal connection | Must remain unconnected; no routing or copper fill allowed. |
| 3 - EN | Enable control input | Active-high logic: ≥1.1 V enables regulation; ≤0.4 V disables output and reduces IQ to 0.5 µA. |
| 4 - BIAS | Bias supply input | Powers internal reference and control circuits; monitored by UVLO (trip = 1.6 V rising). |
| 5 - GND | Analog/digital ground | Common return for IN, OUT, EN, BIAS; thermal pad must be soldered to this net. |
| 6 - IN | Main input supply | Feeds NMOS pass transistor; requires local 1 µF ceramic bypass capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail NMOS architecture | Separates power delivery (VIN→OUT) from control bias (VBIAS), enabling lower dropout than PMOS LDOs and relaxed output capacitor ESR requirements. |
| Built-in monotonic soft-start | Controls VOUT ramp rate to limit inrush current during power-up, preventing input rail collapse in multi-rail systems. |
| VBIAS UVLO with hysteresis | Enables safe startup only when VBIAS ≥ 1.6 V and prevents chatter near threshold via 0.2 V hysteresis. |
| Thermal shutdown with auto-recovery | Shuts down output at +160°C junction temperature and resumes regulation after cooling to +140°C - protects against sustained overload or poor heatsinking. |
| Low-noise, high-PSRR regulation | 40 µVRMS output noise and >65 dB PSRR at 1 kHz enable clean power for ADCs, PLLs, and RF receivers. |
Applications
| Smartphone Application Processor Core Rail | Tablet Camera Sensor Bias Supply |
|---|---|
|
Use Scenario: Powers CPU/GPU core logic operating at 1.05 V in modern smartphone SoCs requiring tight voltage tolerance and fast transient response. IC Role / Device Role / Timing Role: Primary post-regulator delivering stable core voltage downstream of a buck converter, with EN synchronized to processor sleep states. Use Value: Ultra-low dropout enables operation across full Li-ion battery range (4.2 V → 3.0 V), while 0.5 µA shutdown current extends standby time. |
Use Scenario: Supplies clean, low-noise bias to high-resolution CMOS image sensors in tablets, where PSRR and ripple rejection prevent image artifacts. IC Role / Device Role / Timing Role: Low-noise linear regulator placed adjacent to sensor IC, rejecting switching noise from main SoC power rails. Use Value: 65 dB PSRR at 1 kHz and 40 µVRMS noise ensure minimal fixed-pattern noise and improved SNR in low-light capture. |
| Portable DVR Audio Codec Power | STB HDMI Interface I/O Rail |
|
Use Scenario: Provides regulated 1.05 V to audio codec ICs in digital video recorders, where low noise preserves dynamic range and THD+N performance. IC Role / Device Role / Timing Role: Dedicated low-noise LDO for analog audio section, isolated from noisy digital domains via physical layout and VBIAS separation. Use Value: Dual-rail architecture isolates codec bias from main system VIN fluctuations, improving PSRR by >10 dB versus single-rail LDOs. |
Use Scenario: Generates 1.05 V I/O supply for HDMI transmitter/receiver PHYs in set-top boxes, meeting strict voltage accuracy and transient response specs. IC Role / Device Role / Timing Role: Precision voltage source for high-speed interface I/O, with EN controlled by system power manager during hot-plug events. Use Value: ±2% output accuracy over temperature ensures HDMI compliance across industrial ambient range (−40°C to +85°C). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-dropout, dual-rail voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A2025PDBVR | Single-rail 250 mA LDO; no VBIAS input; 170 mV dropout at 350 mA (not rated); 1.05 V not offered - nearest is 1.0 V or 1.1 V. | Lacks VBIAS decoupling; less suitable for ultra-low-VIN scenarios where VIN < VOUT + 1.4 V. | Select only if board space allows higher dropout margin and fixed 1.05 V is not mandatory. |
| MCP1826T-10501E/DB | Single-rail 500 mA LDO; 1.05 V output available; 250 mV dropout at 500 mA; no VBIAS; PSRR peaks at 50 dB @ 1 kHz. | Higher dropout and lower PSRR reduce viability in battery-critical or noise-sensitive designs. | Consider only for cost-sensitive, non-portable applications where thermal and noise constraints are relaxed. |
Compared with TPS7A2025PDBVR and MCP1826T-10501E/DB, the NCP720BMT105TBG uniquely delivers 1.05 V with dual-rail architecture, enabling sub-120 mV dropout and >65 dB PSRR - essential for next-generation portable SoC core rails and imaging subsystems where VBIAS isolation improves system-level noise immunity.
Availability
NCP720BMT105TBG is available at Aetrix Electronics and suitable for smartphone application processor core rails, tablet camera sensor bias supplies, portable DVR audio codec power, STB HDMI interface I/O rails, and other space-constrained, noise-sensitive embedded applications requiring stable component supply across extended temperature ranges.
Supply support for NCP720BMT105TBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, delivering silicon solutions for automotive, industrial, cloud, and IoT markets with emphasis on reliability and sustainability.
The NCP720 series belongs to onsemi's precision low-dropout regulator product line, engineered specifically for battery-powered portable devices requiring ultra-low dropout, low noise, and dual-rail flexibility in miniaturized WDFN packages.
FAQ
What is the nominal output voltage of the NCP720BMT105TBG?
The NCP720BMT105TBG is factory-programmed to deliver a fixed 1.05 V output voltage with ±2% accuracy over the full operating temperature range (−40°C to +125°C). This value is laser-trimmed during production and cannot be adjusted externally - it is confirmed by the "105" suffix in the part number and the JD marking code per the onsemi datasheet ordering table.
Does the NCP720BMT105TBG require an external feedback resistor network?
No, the NCP720BMT105TBG does not require external feedback components. It is a fixed-output voltage regulator with internally trimmed reference and feedback circuitry. The 1.05 V output is set at wafer test and remains stable without any external resistors - simplifying layout and reducing BOM count compared to adjustable LDOs.
What is the minimum required VBIAS voltage for reliable operation of the NCP720BMT105TBG?
The NCP720BMT105TBG requires VBIAS ≥ (VOUT + 1.4 V) = 2.45 V for guaranteed regulation and UVLO release. The datasheet specifies a minimum VBIAS of 2.4 V, but operation below 2.45 V risks instability or premature UVLO shutdown. For robust design, maintain VBIAS ≥ 2.5 V across temperature and tolerance margins.
Can the NCP720BMT105TBG operate with only VIN applied and VBIAS left unconnected?
No - the NCP720BMT105TBG will not regulate if VBIAS is unconnected or below UVLO threshold (1.6 V). The internal reference, error amplifier, and control logic are powered exclusively from VBIAS. Leaving VBIAS floating or disconnected results in undefined behavior, potential latch-up, or permanent damage due to internal node biasing failure.
Is the thermal pad on the WDFN6 package of the NCP720BMT105TBG electrically connected?
Yes, the exposed thermal pad on the NCP720BMT105TBG WDFN6 package is electrically connected to GND and must be soldered to the PCB ground plane. Per the datasheet pin function description and thermal characterization, this connection is mandatory for achieving the specified RJA = 65°C/W and preventing thermal shutdown under 350 mA continuous load.
NCP720BMT105TBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.05V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 1.4V @ 350mA
- Current - Output:
- 350mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 65dB ~ 25dB (1kHz ~ 1MHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WDFN (2x2)
NCP720BMT105TBG FAQ
1.How can I place an order for NCP720BMT105TBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP720BMT105TBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP720BMT105TBG reliable?
The price and inventory of NCP720BMT105TBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP720BMT105TBG is usually 5 days.
3.What payment methods are accepted for NCP720BMT105TBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP720BMT105TBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP720BMT105TBG?
NCP720BMT105TBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP720BMT105TBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP720BMT105TBG?
For technical support, including NCP720BMT105TBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP720BMT105TBG requirements.
6.How does Aetrix verify that NCP720BMT105TBG is sourced from the original manufacturer or authorized distributors?
All NCP720BMT105TBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP720BMT105TBG meets industry standards.
7.What is the process for return or replacement of NCP720BMT105TBG?
All NCP720BMT105TBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP720BMT105TBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP720BMT105TBG part is unused and in its original packaging.
Return procedure for NCP720BMT105TBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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