onsemi NCP720BMT115TBG
- Part No.:
- NCP720BMT115TBG
- Manufacturer:
- onsemi
- Package:
- 6-WDFN Exposed Pad
- Datasheet:
-
NCP720BMT115TBG.pdf
- Description:
- IC REG LINEAR 1.15V 350MA 6WDFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,339
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Product details
Overview
NCP720BMT115TBG from onsemi is a 350 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering fixed 1.15 V output with ±2% accuracy over −40°C to +125°C. It achieves 110 mV typical dropout at full load, supports 0.8–5.5 V input and 2.4–5.5 V bias rails, and operates stably with only a 2.2 µF ceramic output capacitor - ideal for space-constrained, noise-sensitive portable power rails.
For engineers reviewing the NCP720BMT115TBG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail dropout behavior (VIN and VBIAS), ultra-low bias current (80 µA typ), monotonic soft-start, and WDFN6 thermal performance in battery-powered I/O and core logic regulation.
Technical Context
The NCP720BMT115TBG uses an NMOS pass transistor architecture powered by independent VIN and VBIAS supplies - enabling stable regulation even when VIN approaches VOUT (110 mV dropout) while isolating control circuitry from input rail noise. Its internal reference and error amplifier are biased from VBIAS, decoupling PSRR performance from VIN fluctuations.
It integrates undervoltage lockout (UVLO) on VBIAS (1.6 V threshold), thermal shutdown (160°C trip), and current limiting (420–800 mA), with enable logic featuring hysteresis and 0.4 V disable threshold. The device requires no external compensation and maintains stability across temperature and load with minimal output capacitance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.15 V ±2% over −40°C to +125°C - ensures precise core/I/O rail compliance without external feedback. |
| VIN Dropout | 110 mV typical at 350 mA - enables operation down to VIN = 1.26 V, critical for single-cell Li-ion or Li-poly post-regulation. |
| VBIAS Dropout | 1.15 V min (VBIAS – VOUT) - mandates VBIAS ≥ 2.30 V for full-load regulation, supporting shared system bias rails. |
| Bias Current | 80 µA typical (IBIAS) - minimizes auxiliary rail loading in always-on subsystems like RTC or sensor interfaces. |
| PSRR @ 1 kHz | 65 dB (VBIAS), 65 dB (VIN) - suppresses switching noise from DC/DC converters feeding VIN or VBIAS rails. |
| Shutdown Current | 0.5 µA typical (ISHDN) - enables microamp-level system sleep states without compromising wake-up latency. |
| Soft-Start Time | 140 µs to 95% VOUT - prevents inrush into downstream capacitive loads and avoids brown-out in multi-rail systems. |
Pinout & Package
Package: WDFN6 (2 mm × 2 mm, 0.65 mm pitch, Case 511BR), thermally enhanced with exposed pad soldered to PCB ground plane (RJA = 65°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers 1.15 V to load; connects directly to local 2.2 µF ceramic capacitor with minimal trace inductance. |
| 2 - N/C | No internal connection | Must remain unconnected; no routing or copper fill required - avoids parasitic coupling or ESD path risks. |
| 3 - EN | Active-high enable control input | Drives high (>1.1 V) to activate regulator; low (<0.4 V) disables output and reduces ground current to 0.5 µA. |
| 4 - BIAS | Dedicated bias supply for internal circuitry | Powers reference, error amp, and UVLO; must be ≥2.30 V and bypassed with ≥0.1 µF ceramic capacitor. |
| 5 - GND | Power and signal ground reference | Common return for IN, OUT, EN, BIAS; thermal pad must be soldered to solid ground plane for thermal reliability. |
| 6 - IN | Main input voltage supply | Accepts 0.8–5.5 V; requires ≥1 µF ceramic bypass near pin to suppress PCB inductance-induced instability. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail VLDO architecture | Independent VIN and VBIAS inputs allow optimized dropout and PSRR - VIN can be as low as 1.26 V while VBIAS supplies clean control bias. |
| Monotonic soft-start | 140 µs controlled VOUT ramp prevents undershoot/overshoot during power-up and eliminates need for external sequencing. |
| Ultra-low bias current | 80 µA typical IBIAS enables use with high-impedance bias sources (e.g., LDO-fed rails) without degrading efficiency. |
| Stable with small ceramic caps | Guaranteed stability with 2.2 µF–10 µF X5R/X7R ceramics - eliminates need for large tantalum or electrolytic capacitors in thin-profile designs. |
| Integrated protection | Thermal shutdown (160°C), current limit (≥420 mA), and VBIAS UVLO (1.6 V) provide autonomous fault recovery without external circuitry. |
Applications
| Mobile Application Processor I/O Rail | Low-Power Camera Sensor Core |
|---|---|
Use Scenario: Powering 1.15 V I/O banks of application processors in smartphones and tablets where VIN is derived from a buck converter. IC Role / Device Role / Timing Role: Post-regulator providing clean, low-noise, tightly regulated voltage to processor I/O interfaces. Use Value: 65 dB PSRR at 1 kHz rejects switching noise from upstream DC/DC, preventing data corruption and timing jitter in high-speed interfaces. |
Use Scenario: Supplying 1.15 V core voltage to image sensors in compact camera modules with strict thermal and area constraints. IC Role / Device Role / Timing Role: Low-dropout linear regulator delivering stable bias under variable load transients during frame capture. Use Value: 110 mV dropout enables operation from partially discharged batteries, extending usable runtime without brown-out resets. |
| Set-Top Box Memory Interface | Wearable Health Sensor Subsystem |
Use Scenario: Regulating DDR I/O voltage in STBs where board space limits capacitor size and thermal dissipation is constrained. IC Role / Device Role / Timing Role: Fixed-output LDO ensuring voltage compliance for memory interface signaling integrity. Use Value: Stable operation with 2.2 µF ceramic capacitor reduces footprint by >50% vs. traditional LDOs requiring ≥10 µF, easing layout in dense PCBs. |
Use Scenario: Powering ultra-low-power analog front-end and ADC in wearable biosensors operating from coin-cell batteries. IC Role / Device Role / Timing Role: Always-on bias rail regulator with sub-µA shutdown current preserving battery life during sleep cycles. Use Value: 0.5 µA shutdown current extends shelf life and operational duration - critical for devices requiring multi-month standby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise, dual-rail LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B115MR-G | Single-rail input (no VBIAS pin); 150 mV dropout at 300 mA; 25 µVRMS noise; WDFN-6 package. | Lacks VBIAS isolation - less effective PSRR when VIN is noisy; unsuitable for split-rail architectures requiring independent bias control. | Select when board uses single clean input rail and cost sensitivity outweighs PSRR/bias flexibility requirements. |
| Richtek RT9080L-115GJ6F | Single-rail input; 100 mV dropout at 300 mA; 45 µVRMS noise; 1.5 µA quiescent current; WDFN-6. | No VBIAS support; higher IQ than NCP720BMT115TBG's 80 µA bias current - increases total system power in bias-critical designs. | Prefer when lowest possible dropout is primary requirement and VBIAS decoupling is not needed for noise isolation. |
Compared with XC6210B115MR-G and RT9080L-115GJ6F, the NCP720BMT115TBG uniquely delivers dual-rail operation with independent VBIAS control, enabling superior PSRR and lower effective bias current in systems where VIN and bias rails originate from different sources - essential for noise-sensitive mixed-signal SoC power domains.
Availability
NCP720BMT115TBG is available at Aetrix Electronics and suitable for mobile processor I/O regulation, camera sensor core powering, set-top box memory interfaces, and wearable health sensor subsystems requiring stable component supply, long-term lifecycle assurance, and Pb-free WDFN6 packaging.
Supply support for NCP720BMT115TBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, and intelligent edge applications.
The NCP720 series belongs to onsemi's precision low-dropout regulator product line, engineered specifically for noise-sensitive, space-constrained portable electronics requiring dual-rail input flexibility and guaranteed stability with minimal external components.
FAQ
What is the nominal output voltage of the NCP720BMT115TBG?
The NCP720BMT115TBG is factory-programmed to deliver a fixed 1.15 V output voltage with ±2% accuracy across −40°C to +125°C junction temperature. This value is laser-trimmed during production and cannot be adjusted externally - it is confirmed by the "115" suffix in the part number and verified in the Electrical Characteristics table of the datasheet.
Does the NCP720BMT115TBG require an external resistor divider for output voltage setting?
No, the NCP720BMT115TBG does not require any external resistors. It is a fixed-output voltage regulator with the 1.15 V value permanently programmed at wafer test. The device has no feedback (FB) pin - all variants in the NCP720 family, including NCP720BMT115TBG, use internal trimming to set VOUT, eliminating external component count and layout variability.
Can the NCP720BMT115TBG operate with VIN below 1.15 V?
No - the NCP720BMT115TBG cannot regulate when VIN falls below VOUT plus dropout voltage. With 110 mV typical dropout at 350 mA, minimum functional VIN is approximately 1.26 V. Below this, the device enters dropout and VOUT tracks VIN minus RDS(on) × ILOAD, losing regulation. The absolute minimum VIN rating is −0.3 V, but functional operation requires VIN ≥ VOUT + VDO_IN.
What is the purpose of the BIAS pin on the NCP720BMT115TBG?
The BIAS pin on the NCP720BMT115TBG supplies dedicated power to the internal reference, error amplifier, and control circuitry - isolating them from VIN noise and enabling high PSRR. It must be ≥2.30 V (VOUT + 1.15 V) for full-load regulation and is monitored by an internal UVLO circuit that disables the regulator if BIAS drops below 1.6 V, preventing erratic behavior during bias rail faults.
Is the NCP720BMT115TBG pin-compatible with other NCP720 variants such as NCP720BMT150TBG?
Yes - all NCP720 variants, including NCP720BMT115TBG and NCP720BMT150TBG, share identical WDFN6 (Case 511BR) pinout, package dimensions, and terminal functions. Only the factory-programmed output voltage differs; electrical characteristics like dropout, PSRR, and bias current remain consistent across the family, enabling drop-in voltage changes without PCB redesign.
NCP720BMT115TBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.15V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 1.4V @ 350mA
- Current - Output:
- 350mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 65dB ~ 25dB (1kHz ~ 1MHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WDFN (2x2)
NCP720BMT115TBG FAQ
1.How can I place an order for NCP720BMT115TBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP720BMT115TBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP720BMT115TBG reliable?
The price and inventory of NCP720BMT115TBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP720BMT115TBG is usually 5 days.
3.What payment methods are accepted for NCP720BMT115TBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP720BMT115TBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP720BMT115TBG?
NCP720BMT115TBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP720BMT115TBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP720BMT115TBG?
For technical support, including NCP720BMT115TBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP720BMT115TBG requirements.
6.How does Aetrix verify that NCP720BMT115TBG is sourced from the original manufacturer or authorized distributors?
All NCP720BMT115TBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP720BMT115TBG meets industry standards.
7.What is the process for return or replacement of NCP720BMT115TBG?
All NCP720BMT115TBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP720BMT115TBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP720BMT115TBG part is unused and in its original packaging.
Return procedure for NCP720BMT115TBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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