onsemi NCP720BMT135TBG
- Part No.:
- NCP720BMT135TBG
- Manufacturer:
- onsemi
- Package:
- 6-WDFN Exposed Pad
- Datasheet:
-
NCP720BMT135TBG.pdf
- Description:
- IC REG LINEAR 1.35V 350MA 6WDFN
- Quantity:
- Payment:

- Shipping:

Inventory:111,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCP720BMT135TBG from onsemi is a 350 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering 1.35 V fixed output with ±2% accuracy over −40°C to +125°C, 110 mV typical dropout at full load, and ultra-low 80 µA bias current - designed for noise-sensitive, space-constrained portable applications including smartphone core rails and camera sensor power.
For engineers reviewing the NCP720BMT135TBG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail operation (VIN/VBIAS), monotonic soft-start, PSRR >65 dB at 1 kHz, stability with 2.2 µF ceramic output capacitor, and WDFN6 thermal pad grounding requirements.
Technical Context
The NCP720BMT135TBG implements a dual-input NMOS-based LDO architecture where VIN supplies the pass element and VBIAS powers internal control circuitry - enabling ultra-low dropout (110 mV @ 350 mA) and reduced output capacitor sensitivity versus PMOS topologies. Its built-in UVLO monitors VBIAS with 1.6 V turn-on threshold and 0.2 V hysteresis.
Regulation relies on a precision voltage reference and error amplifier driving the NMOS gate; soft-start ensures monotonic VOUT rise to limit inrush current, while thermal shutdown activates at +160°C and resets at +140°C. PSRR exceeds 65 dB at 1 kHz for both VIN and VBIAS inputs, supporting clean power delivery in mixed-signal SoC domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.35 V ±2% over −40°C to +125°C - ensures stable core voltage for low-power processors and image sensors. |
| VIN Range | 0.8 V to 5.5 V - supports direct battery input down to single-cell Li-ion or multi-cell alkaline configurations. |
| VBIAS Range | 2.4 V to 5.5 V - enables use of higher-voltage auxiliary rails (e.g., 3.3 V or 5 V system supplies) to bias control circuitry independently. |
| VIN Dropout | 110 mV typical at 350 mA - allows regulation with minimal headroom, critical for extending battery runtime in portable devices. |
| Bias Current | 80 µA typical (0.5 µA in shutdown) - minimizes quiescent power draw from VBIAS rail, preserving standby efficiency. |
| PSRR @ 1 kHz | 65 dB (VIN), 70 dB (VBIAS) - suppresses switching noise from upstream DC/DC converters feeding VIN or VBIAS. |
| Stability | Guaranteed with 2.2 µF ceramic output capacitor - eliminates need for bulky tantalum or electrolytic capacitors in compact layouts. |
Pinout & Package
Package: WDFN6 2 mm × 2 mm, 0.65 mm pitch, exposed thermal pad (Case 511BR). Thermal pad must be soldered to PCB ground plane for RJA = 65°C/W performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers stable 1.35 V to load; requires low-ESR ceramic capacitor directly connected. |
| 2 - N/C | No internal connection | Must remain unconnected; no routing or copper fill allowed. |
| 3 - EN | Enable control input | Active-high logic: ≥1.1 V enables regulator; ≤0.4 V disables with 0.5 µA shutdown current. |
| 4 - BIAS | Bias supply for internal circuitry | Powers reference, error amp, and control logic; monitored by UVLO (1.6 V turn-on). |
| 5 - GND | Analog/digital ground reference | Common return for IN, OUT, EN, BIAS; thermal pad must connect to same ground plane. |
| 6 - IN | Main input voltage supply | Feeds NMOS pass transistor; dropout defined as (VIN – VOUT) with VBIAS held sufficient. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail NMOS architecture | Separates power path (VIN→OUT) from control bias (VBIAS), enabling lower dropout and improved PSRR vs. single-rail LDOs. |
| Monotonic soft-start | Controls VOUT ramp rate to prevent undershoot/overshoot during startup, eliminating need for external sequencing. |
| Ultra-low bias current | 80 µA typical active current reduces loading on auxiliary VBIAS rails, critical for multi-rail battery systems. |
| Thermal shutdown with hysteresis | +160°C shutdown / +140°C reset prevents latch-up during transient overload or poor heatsinking. |
| High PSRR at audio frequencies | 70 dB rejection at 1 kHz on VBIAS suppresses noise coupling from shared system supplies into sensitive analog blocks. |
Applications
| Smartphone Core Rail | Digital Camera Sensor Power |
|---|---|
Use Scenario: Powering application processor I/O or GPU cores requiring tight voltage tolerance and low noise in slim form factor designs. IC Role / Device Role / Timing Role: Primary post-regulator converting switched-mode output to clean, stable 1.35 V for digital logic domains. Use Value: 110 mV dropout extends usable battery range; ±2% accuracy ensures reliable timing margin under temperature and load variation. | Use Scenario: Supplying CMOS image sensor analog and digital rails where switching noise from DC/DC converters must be suppressed. IC Role / Device Role / Timing Role: Low-noise linear regulator filtering high-frequency ripple from upstream buck converter outputs. Use Value: 70 dB PSRR at 1 kHz on VBIAS rejects noise from shared 3.3 V system rail, preserving image SNR and reducing fixed-pattern noise. |
| Tablet Application Processor I/O | STB Memory Interface Power |
Use Scenario: Delivering regulated 1.35 V to DDR I/O buffers in tablet SoCs where layout space is constrained and thermal dissipation limited. IC Role / Device Role / Timing Role: Compact-area LDO placed near processor package to minimize trace inductance and voltage droop. Use Value: WDFN6 2 mm × 2 mm footprint with thermal pad enables 350 mA delivery in <4 mm² area; 2.2 µF ceramic stability simplifies BOM. | Use Scenario: Powering LPDDR4 memory interface in set-top boxes requiring fast transient response and low output impedance. IC Role / Device Role / Timing Role: Local point-of-load regulator responding to dynamic current demands of memory read/write bursts. Use Value: 140 µs startup time ensures rapid power-up after wake-from-sleep; 420–800 mA current limit handles memory peak loads without shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-dropout, dual-rail voltage regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B135MR-G | Single-rail (VIN-only) 1.35 V LDO; 250 mA rating; no VBIAS input; 200 mV dropout at full load. | Lacks independent bias rail - unsuitable where VBIAS decoupling from VIN is required for noise isolation. | Select when board space permits larger dropout margin and system lacks dedicated VBIAS source. |
| Richtek RT9080L-135GJ6 | Single-rail 1.35 V LDO; 500 mA rating; 150 mV dropout; no VBIAS; includes foldback current limit. | Higher current capability but no dual-rail architecture - cannot replicate NCP720BMT135TBG's VBIAS PSRR advantage. | Choose for higher load current needs where VBIAS independence is not required and 150 mV dropout is acceptable. |
Compared with XC6210B135MR-G and RT9080L-135GJ6, the NCP720BMT135TBG uniquely delivers dual-rail operation enabling superior noise rejection via separate VBIAS supply, lower dropout (110 mV), and tighter output accuracy (±2%) - making it optimal for noise-critical, battery-sensitive portable SoC power domains.
Availability
NCP720BMT135TBG is available at Aetrix Electronics and suitable for smartphone core rails, digital camera sensor power, and tablet application processor I/O requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for NCP720BMT135TBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, with leadership in power management, analog, sensing, and connectivity solutions.
The NCP720 series belongs to onsemi's precision low-noise LDO portfolio, engineered specifically for dual-rail, ultra-low dropout operation in battery-powered portable electronics demanding high PSRR and minimal board area.
FAQ
What is the nominal output voltage of the NCP720BMT135TBG?
The NCP720BMT135TBG is factory-programmed for a fixed 1.35 V output voltage, with guaranteed accuracy of ±2% over the full operating junction temperature range of −40°C to +125°C. This value is laser-trimmed during production and cannot be adjusted externally. The "135" in the part number explicitly denotes the 1.35 V nominal output, consistent with onsemi's NCP720 voltage variant naming convention.
Does the NCP720BMT135TBG require an external VBIAS supply, and what voltage range is supported?
Yes, the NCP720BMT135TBG requires a separate VBIAS supply connected to Pin 4, which powers its internal reference and control circuitry. VBIAS must be between 2.4 V and 5.5 V - specifically, (VOUT + 1.4 V) or 2.5 V, whichever is greater. For the NCP720BMT135TBG's 1.35 V output, minimum VBIAS is 2.75 V. Operation outside this range may trigger UVLO or degrade regulation performance.
What is the maximum continuous output current and dropout voltage specification for the NCP720BMT135TBG?
The NCP720BMT135TBG delivers up to 350 mA continuous output current. Its VIN dropout voltage is specified at 110 mV typical (200 mV max) at 350 mA load, defined as (VIN – VOUT) while maintaining regulation - provided VBIAS is within specification. This ultra-low dropout enables operation with minimal input-to-output differential, extending battery life in portable systems.
Can the NCP720BMT135TBG operate without connecting the EN pin?
Yes, the NCP720BMT135TBG can operate with EN unconnected only if tied permanently high - either to VIN or VBIAS - since it is an active-high enable input. Leaving EN floating is not recommended due to potential noise-induced toggling. If enable functionality is unused, hard-wiring EN to VIN or VBIAS ensures reliable startup; the NCP720BMT135TBG draws only ~20 µA per volt of nominal output from VIN when enabled.
Is the NCP720BMT135TBG stable with ceramic output capacitors, and what value is recommended?
Yes, the NCP720BMT135TBG is specifically designed for stability with ceramic output capacitors. onsemi guarantees stability with 2.2 µF to 10 µF effective capacitance - 2.2 µF is the minimum recommended value, and it must be placed directly at the OUT pin with minimal trace length and no vias. The device does not require ESR damping, simplifying layout and reducing BOM cost compared to older LDO architectures.
NCP720BMT135TBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.35V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 1.4V @ 350mA
- Current - Output:
- 350mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 65dB ~ 25dB (1kHz ~ 1MHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WDFN (2x2)
NCP720BMT135TBG FAQ
1.How can I place an order for NCP720BMT135TBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP720BMT135TBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP720BMT135TBG reliable?
The price and inventory of NCP720BMT135TBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP720BMT135TBG is usually 5 days.
3.What payment methods are accepted for NCP720BMT135TBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP720BMT135TBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP720BMT135TBG?
NCP720BMT135TBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP720BMT135TBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP720BMT135TBG?
For technical support, including NCP720BMT135TBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP720BMT135TBG requirements.
6.How does Aetrix verify that NCP720BMT135TBG is sourced from the original manufacturer or authorized distributors?
All NCP720BMT135TBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP720BMT135TBG meets industry standards.
7.What is the process for return or replacement of NCP720BMT135TBG?
All NCP720BMT135TBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP720BMT135TBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP720BMT135TBG part is unused and in its original packaging.
Return procedure for NCP720BMT135TBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCP720BMT135TBG Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

