onsemi NCP720BMT150TBG
- Part No.:
- NCP720BMT150TBG
- Manufacturer:
- onsemi
- Package:
- 6-WDFN Exposed Pad
- Datasheet:
-
NCP720BMT150TBG.pdf
- Description:
- IC REG LINEAR 1.5V 350MA 6WDFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,294
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Product details
Overview
NCP720BMT150TBG from onsemi is a 350 mA very low dropout (VLDO) CMOS voltage regulator with NMOS pass transistor and separate VBIAS supply, delivering 1.50 V ±2% output with 110 mV typical dropout at full load. It features ultra-low bias current (80 µA typ), built-in soft-start, and stability with 2.2 µF ceramic output capacitor-designed for noise-sensitive, space-constrained portable applications including smartphone core logic rails.
For engineers reviewing the NCP720BMT150TBG datasheet, pinout, applications, or equivalent options, key selection criteria include dual-rail operation (VIN/VBIAS), monotonic startup, PSRR >65 dB at 1 kHz, thermal shutdown at +160°C, and WDFN6 2 mm × 2 mm package compatibility with high-density PCB layouts.
Technical Context
The NCP720BMT150TBG implements a dual-input NMOS-based LDO architecture: VIN supplies the pass element while VBIAS powers internal control circuitry-including reference, error amplifier, and enable logic-enabling independent optimization of power path and bias efficiency. This separation allows stable regulation even when VIN approaches VOUT.
Its simplified block diagram confirms dedicated UVLO on VBIAS (1.6 V threshold), current limiting (420–800 mA), and thermal shutdown (+160°C trip / +140°C reset). The device operates across –40°C to +125°C junction temperature and requires no external compensation due to inherent stability with 2.2 µF–10 µF ceramic output capacitance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.50 V ±2% over –40°C to +125°C - ensures precise core voltage for ARM Cortex-A/M series processors. |
| VIN Dropout | 110 mV typ at 350 mA - enables operation down to VIN = 1.61 V, critical for single-cell Li-ion post-regulation. |
| VBIAS Range | 2.4 V to 5.5 V - supports shared bias rail from system PMIC or auxiliary LDO, decoupling bias supply from main input. |
| PSRR @ 1 kHz | 65 dB (VIN), 70 dB (VBIAS) - suppresses switching noise from adjacent DC/DC converters in mixed-signal SoC power domains. |
| Bias Current | 80 µA typ (active), 0.5 µA typ (shutdown) - minimizes quiescent drain on always-on bias sources in battery-backed subsystems. |
| Startup Time | 140 µs to 95% VOUT - ensures monotonic, inrush-limited power-up for FPGA I/O banks and memory interfaces. |
| Thermal Shutdown | +160°C trip, +140°C reset - provides self-recovery protection during sustained overload without requiring external thermal monitoring. |
Pinout & Package
Package: WDFN6 2 mm × 2 mm, 0.65 mm pitch, exposed thermal pad (soldered to GND plane for RJA = 65°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output node | Delivers 1.50 V to load; connects directly to 2.2 µF ceramic capacitor with minimal trace inductance. |
| 2 - N/C | No internal connection | Must remain unconnected; no routing or copper fill required under this pad. |
| 3 - EN | Enable control input | Active-high logic (VEN(HI) = 1.1 V min); internal hysteresis prevents chatter during slow-rising enable signals. |
| 4 - BIAS | Bias supply for internal circuitry | Powers reference and error amp; monitored by UVLO (1.6 V threshold) - loss of VBIAS disables regulator before VIN collapse. |
| 5 - GND | Analog/digital ground reference | Common return for IN, OUT, BIAS, and EN; thermal pad must be soldered to PCB ground plane. |
| 6 - IN | Main input voltage source | Supplies NMOS pass transistor; accepts 0.8 V–5.5 V but requires VIN ≥ VOUT + 0.5 V for regulation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail NMOS architecture | Enables independent optimization of VIN path (low dropout) and VBIAS path (ultra-low bias current), reducing total system IQ vs. single-rail LDOs. |
| Built-in soft-start | Monotonic VOUT rise limits inrush current to <100 mA during startup - eliminates need for external soft-start circuitry in camera sensor modules. |
| Stability with small ceramics | Guaranteed stable with 2.2 µF–10 µF X5R/X7R ceramic capacitors - eliminates bulk tantalum or electrolytic caps, saving board area and improving reliability. |
| VBIAS UVLO protection | Disables regulator if VBIAS falls below 1.6 V - prevents erratic behavior during bias rail brownout, ensuring clean power sequencing in multi-rail systems. |
| Thermal foldback | Combines current limit (420–800 mA) and thermal shutdown (+160°C) - protects against sustained overload without latch-up, supporting robust field operation. |
Applications
| Smartphone Application Processor Core Rail | Tablet GPU Memory Interface |
|---|---|
Use Scenario: Powers ARM Cortex-A78/A710 CPU cores requiring tightly regulated 1.5 V at up to 350 mA with fast transient response. IC Role / Device Role / Timing Role: Primary post-regulator converting buck converter output (e.g., 2.0 V) to final core voltage; delivers monotonic startup and low-noise supply. Use Value: 110 mV dropout enables operation from partially discharged Li-ion cells (≥3.2 V), while 65 dB PSRR at 1 kHz suppresses switching artifacts from adjacent PMIC buck stages. | Use Scenario: Supplies LPDDR4/5 I/O voltage (VDDQ) in tablet SoCs where layout space is constrained near memory packages. IC Role / Device Role / Timing Role: Low-noise, fixed-output LDO placed adjacent to memory BGA; uses VBIAS from system PMIC to isolate noise-sensitive analog references. Use Value: WDFN6 2 mm × 2 mm footprint fits within tight keep-out zones; 40 µVRMS output noise prevents timing jitter in high-speed memory read/write cycles. |
| Industrial Camera Sensor Bias | STB SoC I/O Domain Regulator |
Use Scenario: Provides clean 1.5 V bias to CMOS image sensor analog front-end (AFE) in surveillance cameras operating at –40°C to +85°C. IC Role / Device Role / Timing Role: Noise-suppressing LDO decoupling sensor AFE from noisy digital subsystems; enabled only during active imaging via EN pin. Use Value: 70 dB VBIAS PSRR rejects ripple from shared PMIC bias rail; 0.5 µA shutdown current extends battery life in motion-triggered recording modes. | Use Scenario: Regulates I/O voltage for set-top box SoC peripherals including HDMI PHY, USB transceivers, and SD card interface. IC Role / Device Role / Timing Role: Fixed-output LDO with enable control synchronized to system sleep/wake states; supports hot-plug detection via EN-driven power gating. Use Value: Built-in soft-start prevents bus glitches during USB enumeration; ±2% accuracy ensures compliance with HDMI 2.1 and SD 4.0 voltage tolerance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise, dual-rail LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B152MR-G | Single-rail (VIN-only) 1.5 V LDO; 200 mV dropout at 300 mA; no VBIAS input; 30 µA IQ. | Lacks VBIAS rail independence - unsuitable where bias supply must be isolated from main input or optimized separately. | Select when board space permits larger dropout margin and system lacks dedicated low-noise bias rail. |
| Richtek RT9080AL-15GJ5 | Dual-rail LDO with 1.5 V output; 120 mV dropout; 60 µA bias current; no thermal shutdown hysteresis (reset at +135°C). | Slightly higher dropout and narrower thermal hysteresis window - may cycle more frequently under marginal thermal conditions. | Select when cost sensitivity outweighs need for +20°C thermal hysteresis margin and 0.5 µA shutdown current. |
Compared with XC6210B152MR-G and RT9080AL-15GJ5, the NCP720BMT150TBG uniquely combines VBIAS-enabled bias isolation, 110 mV dropout, and +20°C thermal hysteresis - making it optimal for battery-powered, thermally dense portable designs requiring guaranteed monotonic startup and ultra-low bias leakage.
Availability
NCP720BMT150TBG is available at Aetrix Electronics and suitable for smartphone processor core rails, tablet GPU memory interfaces, industrial camera sensor biasing, and STB SoC I/O domain regulation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NCP720BMT150TBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NCP720BMT150TBG belongs to onsemi's VLDO linear regulator product line, engineered specifically for noise-sensitive, space-constrained portable electronics requiring dual-rail operation, ultra-low dropout, and guaranteed stability with miniature ceramic capacitors.
FAQ
What is the nominal output voltage of the NCP720BMT150TBG?
The NCP720BMT150TBG is factory-programmed for a fixed nominal output voltage of 1.50 V, with ±2% accuracy maintained over the full operating junction temperature range of –40°C to +125°C. This value is laser-trimmed during production and cannot be adjusted externally. The "150" in the part number explicitly denotes the 1.50 V output, consistent with onsemi's NCP720 family voltage coding convention.
Does the NCP720BMT150TBG require an external bias supply, and what voltage range is acceptable?
Yes, the NCP720BMT150TBG requires a separate VBIAS supply connected to Pin 4. The acceptable VBIAS range is 2.4 V to 5.5 V, with minimum functional operation at (VOUT + 1.4 V) = 2.9 V or 2.5 V - whichever is greater. This dual-rail architecture isolates internal control circuitry from the main VIN path, enabling ultra-low bias current (80 µA typ) and high PSRR on the bias rail.
Can the NCP720BMT150TBG operate with a 1.8 V input voltage?
No - the NCP720BMT150TBG requires VIN ≥ VOUT + 0.5 V = 2.0 V for regulation. At 1.8 V input, the device enters dropout and cannot maintain 1.50 V output. Its minimum functional VIN is 2.0 V under load; typical operation starts at VIN = 2.1 V to accommodate the 110 mV typical dropout. For sub-2.0 V inputs, a different regulator with lower dropout or higher VOUT/NOM ratio is required.
Is the NCP720BMT150TBG compatible with 2.2 µF ceramic output capacitors, and why is this significant?
Yes, the NCP720BMT150TBG is fully stable with a single 2.2 µF X5R or X7R ceramic capacitor on the OUT pin - no additional ESR or external compensation is needed. This eliminates bulky, less-reliable tantalum or aluminum electrolytic capacitors, reduces PCB area by >50%, and improves long-term reliability in portable devices subjected to thermal cycling and mechanical shock.
What happens to the NCP720BMT150TBG when the EN pin is left floating?
The EN pin of the NCP720BMT150TBG must not be left floating: it has no internal pull-up or pull-down. If unconnected, the device behavior is undefined and may oscillate or fail to enable reliably. Per the datasheet, unused EN pins must be tied directly to VIN or VBIAS. For default-on operation, connect EN to VIN through a low-impedance trace; for controlled enable, drive with a clean logic signal referenced to GND.
NCP720BMT150TBG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 1.4V @ 350mA
- Current - Output:
- 350mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- 65dB ~ 25dB (1kHz ~ 1MHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WDFN (2x2)
NCP720BMT150TBG FAQ
1.How can I place an order for NCP720BMT150TBG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCP720BMT150TBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCP720BMT150TBG reliable?
The price and inventory of NCP720BMT150TBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCP720BMT150TBG is usually 5 days.
3.What payment methods are accepted for NCP720BMT150TBG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCP720BMT150TBG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCP720BMT150TBG?
NCP720BMT150TBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCP720BMT150TBG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCP720BMT150TBG?
For technical support, including NCP720BMT150TBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCP720BMT150TBG requirements.
6.How does Aetrix verify that NCP720BMT150TBG is sourced from the original manufacturer or authorized distributors?
All NCP720BMT150TBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCP720BMT150TBG meets industry standards.
7.What is the process for return or replacement of NCP720BMT150TBG?
All NCP720BMT150TBG units undergo pre-shipment inspection (PSI). If there is an issue with NCP720BMT150TBG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCP720BMT150TBG part is unused and in its original packaging.
Return procedure for NCP720BMT150TBG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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