Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

onsemi NCV59745AMW250TAG

Name: NCV59745AMW250TAG
Brand: onsemi
SKU: NCV59745AMW250TAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: NCV59745AMW250TAG

Manufacturer:: onsemi

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: 20-VFQFN Exposed Pad

Datasheet:: NCV59745AMW250TAG.pdf

Description:: QFN20 4X4 0.5PP STEP CUT WETTABL

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,988

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

NCV59745AMW250TAG from onsemi is a fixed-output, dual-rail, very low dropout (VLDO) linear voltage regulator delivering up to 3.0 A output current with 105 mV typical dropout at full load, 0.25% typical output accuracy over line and load, and 6 µV_RMS output noise (10 Hz–100 kHz). It features programmable soft-start, open-drain Power Good output, and is qualified for automotive applications per AEC-Q100. It powers noise-sensitive high-speed digital loads including FPGAs and SerDes in point-of-load configurations.

For engineers reviewing the NCV59745AMW250TAG datasheet, pinout, applications, or equivalent options, key selection criteria include its 2.50 V fixed output, QFNW20 4.0 mm × 4.0 mm wettable flank package, bias rail architecture (V_BIAS = 2.2–5.5 V), PSRR of 75 dB at 1 kHz, and active output discharge capability (NCV59745A variant).

Technical Context

The NCV59745AMW250TAG uses an NMOS pass transistor architecture powered by separate VIN and VBIAS rails-enabling ultra-low dropout operation while decoupling loop stability from output capacitance selection. Its internal controller integrates undervoltage lockout (UVLO), thermal shutdown (TSD) at +165°C, and enable pin hysteresis (100 mV) with deglitch filtering.

It implements programmable soft-start via external CSS capacitor (t_SS = C_SS × 0.13 ms), delivers active output discharge through a 600 Ω internal resistor when EN is low (NCV59745A feature), and provides precise power sequencing via open-drain PG output with 82–96% V_OUT trip threshold and 3% hysteresis.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	Fixed 2.50 V - eliminates external feedback network; ensures stable rail for I/O or core logic requiring tight tolerance.
Max Output Current	3.0 A - supports high-current FPGA I/O banks or ASIC subsystems without external current boosting.
Dropout Voltage	105 mV typ. at 3 A - enables regulation from VIN as low as 2.605 V, critical for battery-adjacent or multi-rail systems.
Output Accuracy	±0.3% typ. over line/load/temp - guarantees timing margin integrity for high-speed interfaces like DDR or PCIe.
Output Noise	6 µV_RMS (10 Hz–100 kHz) - meets stringent analog/RF supply requirements for VCOs, ADCs, and imaging sensors.
PSRR	75 dB at 1 kHz - suppresses switching noise from upstream DC-DC converters feeding VIN or VBIAS rails.
Soft-Start Time	Programmable (0.35–13 ms) via CSS capacitor - prevents inrush into large bulk capacitance (e.g., 330 µF tantalum + MLCC stacks).
Power Good Threshold	88% V_OUT typ. with 3% hysteresis - enables reliable power sequencing with downstream devices requiring monotonic ramp detection.

Pinout & Package

NCV59745AMW250TAG is housed in a thermally enhanced QFNW20 (4.0 mm × 4.0 mm, 0.5 mm pitch) package with exposed thermal pad. The wettable flank design supports automated optical inspection (AOI) of solder joints.

Pin/Terminal	Circuit Role	Design Meaning
IN (Pins 15–17)	Main input supply rail	Accepts 0.8–5.5 V; supplies NMOS pass element; dropout defined relative to VOUT.
BIAS (Pin 12)	Bias supply for control circuitry	Provides 2.2–5.5 V to error amplifier, reference, and internal logic; enables independent rail optimization.
OUT (Pins 1, 19, 20)	Regulated output	Delivers 2.50 V @ up to 3.0 A; requires ≥10 µF effective ceramic output capacitance.
SNS (Pin 2)	Remote output voltage sense	Enables Kelvin sensing to compensate PCB trace IR drop; must not float.
PG (Pin 4)	Open-drain Power Good indicator	Signals VOUT validity; requires external 10–100 kΩ pull-up; supports system-level power sequencing.
EN (Pin 14)	Enable control input	Active-high logic; 1.1 V threshold with 100 mV hysteresis; deglitched for noise immunity.
SS (Pin 13)	Soft-start timing node	Charged by 6.2 µA internal current; external CSS capacitor sets startup ramp time.
GND (Pins 8, 18)	Signal and power ground	Dual GND pins reduce impedance; thermal pad must be soldered to PCB ground plane.
NC (Pins 3, 5–7, 9–11)	No connection	True NC pins; may be left floating or tied to GND for improved thermal conduction.

Key Features

Feature	Design Value
Dual-rail architecture (VIN + VBIAS)	Decouples pass device drive from output regulation-enables stable operation with low-ESR ceramic capacitors and extends usable input range.
Active output discharge (NCV59745A)	600 Ω internal discharge path pulls VOUT to GND during shutdown-ensures clean restart from 0 V in multi-rail sequenced systems.
Programmable soft-start	External CSS capacitor sets monotonic ramp time (0.35–13 ms)-prevents inrush-induced voltage droop on shared input rails.
High PSRR (75 dB @ 1 kHz)	Rejects noise from switching regulators feeding VIN or VBIAS-critical for powering SerDes PLLs and RF front-ends.
AEC-Q100 qualified	Validated for automotive temperature range (−40°C to +125°C junction) and reliability stress tests-supports ADAS and infotainment ECUs.
Wettable flank QFNW20	Facilitates AOI of solder fillets on all perimeter pins-improves manufacturing yield in automotive-grade SMT lines.

Applications

High-Speed FPGA I/O Supply	FPGA Core & Memory Interface
Use Scenario: Powering bank-specific I/O rails (e.g., LVDS, SSTL-18) in Xilinx Kintex or Intel Stratix FPGAs where rail monotonicity and low noise are mandatory. IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering stable 2.50 V with <100 mV dropout and <6 µV RMS noise to meet I/O timing jitter budgets. Use Value: Enables reliable high-speed data capture at >1 Gbps by suppressing supply-induced jitter and supporting fast, controlled power-up sequencing.	Use Scenario: Supplying memory interface circuits (DDR3/4 termination, PHY bias) adjacent to FPGA or SoC die where transient response and PSRR directly impact signal integrity. IC Role / Device Role / Timing Role: Low-noise, high-PSRR LDO regulating 2.50 V for memory VTT or VREF rails; complements main DC-DC converter. Use Value: Maintains <±1% VTT accuracy under 0–3 A load transients, reducing bit error rates in high-density memory channels.
Automotive Camera Sensor Bias	Industrial Imaging Signal Chain
Use Scenario: Providing clean 2.50 V bias to CMOS image sensor analog front-end (AFE) and column ADC in ADAS surround-view cameras. IC Role / Device Role / Timing Role: Low-noise, AEC-Q100-compliant LDO powering sensor analog blocks sensitive to supply ripple and EMI. Use Value: Achieves <6 µV RMS noise and 75 dB PSRR-reducing fixed-pattern noise and enabling >70 dB SNR in 12-bit image capture.	Use Scenario: Regulating precision analog rails (VCO tuning, DAC reference, ADC buffer) in industrial machine vision systems operating in electrically noisy factory environments. IC Role / Device Role / Timing Role: Dual-rail VLDO supplying 2.50 V with independent VBIAS control to isolate analog section from digital switching noise. Use Value: Delivers 0.25% accuracy and excellent transient response-preserving linearity in 16-bit DAC outputs and sub-picosecond clock jitter.

High-Speed FPGA I/O Supply

FPGA Core & Memory Interface

Use Scenario: Powering bank-specific I/O rails (e.g., LVDS, SSTL-18) in Xilinx Kintex or Intel Stratix FPGAs where rail monotonicity and low noise are mandatory.

IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering stable 2.50 V with <100 mV dropout and <6 µV RMS noise to meet I/O timing jitter budgets.

Use Value: Enables reliable high-speed data capture at >1 Gbps by suppressing supply-induced jitter and supporting fast, controlled power-up sequencing.

Use Scenario: Supplying memory interface circuits (DDR3/4 termination, PHY bias) adjacent to FPGA or SoC die where transient response and PSRR directly impact signal integrity.

IC Role / Device Role / Timing Role: Low-noise, high-PSRR LDO regulating 2.50 V for memory VTT or VREF rails; complements main DC-DC converter.

Use Value: Maintains <±1% VTT accuracy under 0–3 A load transients, reducing bit error rates in high-density memory channels.

Automotive Camera Sensor Bias

Industrial Imaging Signal Chain

Use Scenario: Providing clean 2.50 V bias to CMOS image sensor analog front-end (AFE) and column ADC in ADAS surround-view cameras.

IC Role / Device Role / Timing Role: Low-noise, AEC-Q100-compliant LDO powering sensor analog blocks sensitive to supply ripple and EMI.

Use Value: Achieves <6 µV RMS noise and 75 dB PSRR-reducing fixed-pattern noise and enabling >70 dB SNR in 12-bit image capture.

Use Scenario: Regulating precision analog rails (VCO tuning, DAC reference, ADC buffer) in industrial machine vision systems operating in electrically noisy factory environments.

IC Role / Device Role / Timing Role: Dual-rail VLDO supplying 2.50 V with independent VBIAS control to isolate analog section from digital switching noise.

Use Value: Delivers 0.25% accuracy and excellent transient response-preserving linearity in 16-bit DAC outputs and sub-picosecond clock jitter.

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise, high-current LDO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS7A8300RGRT	3.0 A, 2.5 V fixed, 13 µV_RMS noise, no VBIAS rail, non-AEC-Q100	Targets industrial/commercial high-performance analog; lacks automotive qualification and bias rail flexibility	Select when AEC-Q100 is unnecessary and lower cost is prioritized over ultra-low noise.
NCP1117ST2R5T3G	1.0 A, 2.5 V fixed, 42 µV_RMS noise, single-rail, AEC-Q100 option available	Lower current/noise performance; suitable for auxiliary or low-power sensor rails only	Choose only for space-constrained, cost-sensitive designs where 3 A and 6 µV_RMS are not required.

Compared with TPS7A8300RGRT and NCP1117ST2R5T3G, the NCV59745AMW250TAG uniquely combines automotive qualification, dual-rail architecture, 3 A capability, and industry-leading 6 µV_RMS noise-making it the sole fit for safety-critical, high-speed imaging and FPGA power delivery where both performance and compliance are non-negotiable.

Availability

NCV59745AMW250TAG is available at Aetrix Electronics and suitable for automotive ADAS camera modules, FPGA-based industrial controllers, and high-speed telecom SerDes point-of-load regulation requiring stable component supply across extended temperature and lifecycle demands.

Supply support for NCV59745AMW250TAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics for automotive, industrial, cloud, medical, and IoT applications.

The NCV59745AMW250TAG belongs to onsemi's NCV automotive-grade LDO family, engineered specifically for noise-sensitive, high-current point-of-load regulation in safety-critical vehicle systems-including camera modules, radar processors, and domain controllers.

FAQ

What is the output voltage tolerance of the NCV59745AMW250TAG over temperature and load?

The NCV59745AMW250TAG delivers ±0.3% typical output voltage accuracy across −40°C to +125°C junction temperature, 50 mA to 3.0 A load, and V_BIAS from 2.4 V to 5.25 V. This is confirmed in Table 5 of the datasheet under "V_OUT Accuracy" with min/max bounds of −1.0% to +1.0%. The tight tolerance ensures reliable operation of 2.5 V I/O standards such as SSTL and HSTL without external trimming.

Does the NCV59745AMW250TAG require an external capacitor on the SS pin for basic operation?

No-the NCV59745AMW250TAG starts up with a minimum 0.35 ms soft-start time when the SS pin is left open (no capacitor). An external CSS capacitor is optional and used only to extend soft-start duration (e.g., 10 nF yields ~1.3 ms). The device remains fully functional without it, but adding CSS improves inrush control in systems with large output capacitance.

Is the NCV59745AMW250TAG compatible with ceramic output capacitors, and what is the minimum recommended value?

Yes-the NCV59745AMW250TAG is explicitly designed for stability with ceramic output capacitors. The datasheet specifies a minimum effective capacitance of 10 µF (Table 4 and Applications Information), and confirms stability up to 1000 µF. Multiple parallel ceramics (e.g., 3×10 µF MLCCs) are supported and improve high-frequency transient response.

How does the dual-rail architecture (VIN and VBIAS) benefit system design compared to single-rail LDOs?

The dual-rail architecture allows independent optimization: VIN can be derived from a noisy, high-efficiency DC-DC converter (e.g., 3.3 V), while VBIAS is supplied from a cleaner, lower-noise source (e.g., 5.0 V LDO). This separation improves PSRR, reduces sensitivity to VIN ripple, and enables lower dropout than possible with single-rail topologies-especially critical below 3.0 V input.

What thermal performance can be expected from the NCV59745AMW250TAG in a standard 2-layer PCB layout?

In a JEDEC-standard high-K board (2 oz. copper top/bottom, 3×3 thermal via array to inner ground plane), the NCV59745AMW250TAG exhibits R_θJA = 40°C/W and R_θJB = 3.6°C/W (Table 3). At 3.0 A load with 2.5 V output and 3.3 V VIN, power dissipation is ~2.4 W-resulting in ~96°C rise above ambient. To stay within the +125°C max junction limit, ambient must remain ≤29°C unless enhanced cooling is applied.

NCV59745AMW250TAG Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: -

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 1

Voltage - Input (Max):: 5.5V

Voltage - Output (Min/Fixed):: 2.5V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.195V @ 3A

Current - Output:: 3A

Current - Quiescent (Iq):: 3 mA

Current - Supply (Max):: -

PSRR:: -

Control Features:: Current Limit, Enable, Soft Start

Protection Features:: Over Current, Over Temperature, Under Voltage Lockout (UVLO)

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount, Wettable Flank

Supplier Device Package:: 20-QFNW (4x4)

NCV59745AMW250TAG FAQ

1.How can I place an order for NCV59745AMW250TAG through Aetrix?

Please submit a Request for Quotation (RFQ) for NCV59745AMW250TAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for NCV59745AMW250TAG reliable?

The price and inventory of NCV59745AMW250TAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCV59745AMW250TAG is usually 5 days.

3.What payment methods are accepted for NCV59745AMW250TAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCV59745AMW250TAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for NCV59745AMW250TAG?

NCV59745AMW250TAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your NCV59745AMW250TAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for NCV59745AMW250TAG?

For technical support, including NCV59745AMW250TAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCV59745AMW250TAG requirements.

6.How does Aetrix verify that NCV59745AMW250TAG is sourced from the original manufacturer or authorized distributors?

All NCV59745AMW250TAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCV59745AMW250TAG meets industry standards.

7.What is the process for return or replacement of NCV59745AMW250TAG?

All NCV59745AMW250TAG units undergo pre-shipment inspection (PSI). If there is an issue with NCV59745AMW250TAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The NCV59745AMW250TAG part is unused and in its original packaging.

Return procedure for NCV59745AMW250TAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…