onsemi NCV59801CMTWADJTAG
- Part No.:
- NCV59801CMTWADJTAG
- Manufacturer:
- onsemi
- Package:
- 6-WDFN Exposed Pad
- Datasheet:
-
NCV59801CMTWADJTAG.pdf
- Description:
- LDO, 1A, AUTOMOTIVE, LOW NOISE,
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NCV59801CMTWADJTAG from onsemi is an automotive-grade 1 A adjustable LDO regulator with ±0.7% initial accuracy at 25°C, 85 dB PSRR at 1 kHz, and 120 mV typical dropout at 3.3 V output/1 A load. It features Power Good open-collector output, active output discharge (250 Ω), and 5 mV/s controlled slew rate - designed for RF and analog power rails in telematics and infotainment systems.
For engineers reviewing the NCV59801CMTWADJTAG datasheet, pinout, applications, or equivalent options, this page delivers verified package mapping (WDFNW6 2 mm × 2 mm), validated FB/EN/PG functionality, thermal performance (RJA = 60 °C/W), noise (10 µVRMS fixed version reference), and automotive qualification (AEC-Q100).
Technical Context
The NCV59801CMTWADJTAG implements a high-PSRR, low-noise LDO architecture with internal reference voltage of 0.6 V (±1% over temperature/load), enabling precise output regulation down to 0.6 V via external resistor divider on FB pin. Its EN-controlled shutdown draws only 0.1 µA typical, and PG output provides 95% rising / 90% falling threshold detection with 9 µs blanking time.
Thermal design leverages the exposed pad (RJC(bot) = 6.9 °C/W) and supports stable operation with 4.7 µF ceramic capacitors on both IN and OUT. The device integrates current limiting (1.5–1.7 A), thermal shutdown (165 °C), and soft-start via 5 mV/s slew control - all optimized for automotive power sequencing and noise-sensitive analog subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 1 A continuous - supports high-current analog/RF ICs without derating at TA ≤ 85°C with proper PCB copper. |
| Reference Voltage | 0.6 V ±1% - sets minimum output and defines feedback ratio for adjustable configurations. |
| Accuracy | ±0.7% at 25°C, ±1% over −40°C to +125°C - ensures tight voltage margin for 1.2 V, 1.8 V, or 3.3 V domain supplies. |
| PSRR | 85 dB @ 1 kHz - suppresses switching noise from upstream DC-DC converters feeding sensitive ADCs or PLLs. |
| Dropout Voltage | 120 mV @ 3.3 V/1 A - enables operation from 3.42 V input, critical for battery-sourced 3.3 V rails during cold-crank. |
| Noise | 10 µVRMS (10 Hz–100 kHz, fixed version baseline) - translates to ~60 µVRMS at 3.6 V via 0.6 V reference, acceptable for audio codecs. |
| Slew Rate | 5 mV/s - controls inrush during power-up, preventing false resets in connected MCUs during hot-plug events. |
| Quiescent Current | 35 µA typical - sustains low-power sleep modes in always-on telematics modules without draining battery. |
Pinout & Package
NCV59801CMTWADJTAG uses the WDFNW6 2 mm × 2 mm × 0.75 mm package (Case 511DW), with wettable flanks and exposed thermal pad tied to GND. Pin count: 6 terminals, including dedicated FB for adjustable output configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OUT) | Regulated output | Delivers final voltage; requires 4.7 µF ceramic capacitor directly adjacent to minimize ESR-induced instability. |
| 2 (FB) | Feedback input | Connects to voltage divider (R1/R2) to set output; input bias <200 nA ensures minimal error contribution. |
| 3 (GND) | Ground reference | Common return for IN, OUT, EN, and PG; must be low-impedance path to thermal pad and system ground plane. |
| 4 (IN) | Input supply | Accepts 1.6–5.5 V; requires ≥4.7 µF X5R/X7R ceramic decoupling to suppress line transients and ripple. |
| 5 (PG) | Power Good open-collector | Sinks up to 10 mA; requires external 10–100 kΩ pull-up to VOUT or VIN for sequencing-aware reset assertion. |
| 6 (EN) | Enable control | Active-high logic: >1 V enables, <0.4 V disables; 0.2 µA pull-down current simplifies MCU GPIO interfacing. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 qualified | Rated for automotive applications (Grade 1: −40°C to +125°C junction), PPAP-capable with unique NCV prefix. |
| Active output discharge | 250 Ω internal FET discharges COUT when disabled - prevents floating voltages that could latch downstream logic. |
| Low-noise regulation | 10 µVRMS noise floor (fixed-version baseline) enables clean supply for RF transceivers and precision ADCs. |
| High PSRR across frequency | 85 dB @ 1 kHz, 75 dB @ 10 kHz, 53 dB @ 100 kHz - maintains signal integrity in mixed-signal SoC power domains. |
| Stable with small ceramics | Guaranteed stability with ≥2.2 µF X5R/X7R output caps; 4.7 µF recommended for full temp/load range robustness. |
| Controlled startup timing | 5 mV/s slew rate + 85 µs dead time ensures predictable power-up sequence for multi-rail systems with strict timing windows. |
Applications
| Telematics Module Power | Infotainment Audio Supply |
|---|---|
Use Scenario: Powers LTE modem, GNSS receiver, and CAN controller in vehicle telematics units under varying battery conditions (9–16 V). IC Role / Device Role / Timing Role: Primary 3.3 V or 1.8 V LDO delivering regulated rail with fast transient response and low noise for RF front-end and digital baseband. Use Value: 85 dB PSRR rejects noise from buck converters; 120 mV dropout ensures operation during cold-crank (≥6.5 V battery sag); AEC-Q100 compliance guarantees field reliability. |
Use Scenario: Supplies low-noise 1.2 V or 1.8 V to audio codec and DSP in head-unit infotainment systems. IC Role / Device Role / Timing Role: Clean analog supply LDO with 10 µVRMS noise baseline and 5 mV/s controlled ramp to prevent pop/click during power-up. Use Value: Active discharge clears residual charge before mute/unmute transitions; ±0.7% accuracy maintains THD+N spec across temperature. |
| Instrument Cluster Display | ADAS Camera Interface |
Use Scenario: Provides stable 2.5 V or 3.3 V to TFT LCD driver and microcontroller in digital instrument clusters. IC Role / Device Role / Timing Role: Sequenced power rail with PG output signaling readiness to MCU, enabling synchronized display initialization. Use Value: PG blanking (9 µs) avoids false triggers from brief output dips; 35 µA quiescent current extends battery life in key-off monitoring mode. |
Use Scenario: Powers image sensor interface (MIPI CSI-2) and serializer in rear-view or surround-view camera modules. IC Role / Device Role / Timing Role: Low-noise, low-dropout source for 1.2 V sensor core and 2.8 V analog front-end, meeting CISPR-25 Class 5 EMC limits. Use Value: 60 °C/W RJA allows operation at 1 A in sealed enclosures; wettable flanks support automated optical inspection (AOI) of solder joints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NCV8170ADP330T2G | Fixed 3.3 V output, no FB pin, 300 mA max, 120 mV dropout @ 300 mA | Limited to lower-current digital rails; lacks adjustability and PG output | Select when only 3.3 V/300 mA is needed and board space is constrained (1.2 mm × 1.2 mm DFN). |
| TLE42744G | 400 mA, integrated watchdog, higher quiescent current (60 µA), no slew control | Designed for safety-critical MCU supply with reset supervision; not optimized for RF noise rejection | Prefer for ASIL-B functional safety paths where watchdog timeout and fail-safe reset are mandatory. |
Compared with NCV59801CMTWADJTAG, the NCV8170ADP330T2G offers smaller footprint but sacrifices adjustability and PG functionality, while the TLE42744G adds safety features at the cost of noise performance and output flexibility - making NCV59801CMTWADJTAG optimal for high-fidelity analog/RF power domains requiring precision, programmability, and sequencing control.
Availability
NCV59801CMTWADJTAG is available at Aetrix Electronics and suitable for telematics module power, infotainment audio supply, and instrument cluster display applications requiring stable component supply, AEC-Q100 compliance, and long-term automotive lifecycle support.
Supply support for NCV59801CMTWADJTAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensors, and connectivity solutions for automotive, industrial, and cloud infrastructure markets.
The NCV59801 series was developed specifically for automotive power management - emphasizing ultra-low noise, high PSRR, AEC-Q100 qualification, and robust thermal performance in compact WDFNW/DFNW packages.
FAQ
What is the maximum input voltage for NCV59801CMTWADJTAG?
The absolute maximum input voltage for NCV59801CMTWADJTAG is 6 V, but the recommended operating range is 1.6 V to 5.5 V per the datasheet. Exceeding 6 V risks permanent damage. For automotive battery applications, ensure transient suppression (e.g., TVS diode) is used to clamp load-dump spikes above 6 V before the LDO input.
Does NCV59801CMTWADJTAG support adjustable output voltage, and how is it configured?
Yes, NCV59801CMTWADJTAG is the adjustable version - its output voltage is set using an external resistor divider between OUT and FB pins. With VFB = 0.6 V ±1%, the formula is VOUT = 0.6 V × (1 + R1/R2). Use R1/R2 values between 1 kΩ and 220 kΩ to minimize FB bias current error, and avoid exceeding 5.2 V to prevent device damage.
How does the Power Good (PG) output behave during enable/disable transitions in NCV59801CMTWADJTAG?
In NCV59801CMTWADJTAG, the PG output is disabled (high-impedance) when EN is low, so its state depends entirely on the external pull-up voltage. When EN is asserted, PG asserts low after VOUT reaches 95% of nominal (with 18 µs blanking on rise) and deasserts high when VOUT falls below 90% (with 9 µs blanking on fall), providing glitch-immune sequencing feedback.
What thermal performance can be expected from NCV59801CMTWADJTAG in a standard 2-layer PCB layout?
On a standard 2-layer FR-4 board (1 oz Cu, 1 in²), NCV59801CMTWADJTAG in WDFNW6 package achieves RJA = 60 °C/W. At 1 A load with 3.3 V output and 5 V input, power dissipation is ~1.7 W, resulting in ~102 °C junction rise above ambient - well within the 150 °C limit if ambient stays ≤48 °C. Thermal relief vias under the exposed pad are strongly recommended.
Is NCV59801CMTWADJTAG compatible with ceramic capacitors smaller than 4.7 µF?
NCV59801CMTWADJTAG is stable with ≥2.2 µF X5R/X7R ceramic capacitors, but 4.7 µF is specified for guaranteed performance across temperature, load, and input voltage ranges. Using <4.7 µF may degrade line/load transient response and increase output ripple, especially at high temperatures or near dropout - verify stability with actual board-level testing if deviating from the recommended value.
NCV59801CMTWADJTAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 6-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Voltage Dropout (Max):
- 0.407V @ 1A
- Current - Output:
- 1A
- Current - Quiescent (Iq):
- 55 µA
- Current - Supply (Max):
- -
- PSRR:
- -
- Control Features:
- Enable, Soft Start
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 6-WDFNW (2x2)
NCV59801CMTWADJTAG FAQ
1.How can I place an order for NCV59801CMTWADJTAG through Aetrix?
Please submit a Request for Quotation (RFQ) for NCV59801CMTWADJTAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCV59801CMTWADJTAG reliable?
The price and inventory of NCV59801CMTWADJTAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCV59801CMTWADJTAG is usually 5 days.
3.What payment methods are accepted for NCV59801CMTWADJTAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCV59801CMTWADJTAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCV59801CMTWADJTAG?
NCV59801CMTWADJTAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCV59801CMTWADJTAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCV59801CMTWADJTAG?
For technical support, including NCV59801CMTWADJTAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCV59801CMTWADJTAG requirements.
6.How does Aetrix verify that NCV59801CMTWADJTAG is sourced from the original manufacturer or authorized distributors?
All NCV59801CMTWADJTAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCV59801CMTWADJTAG meets industry standards.
7.What is the process for return or replacement of NCV59801CMTWADJTAG?
All NCV59801CMTWADJTAG units undergo pre-shipment inspection (PSI). If there is an issue with NCV59801CMTWADJTAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCV59801CMTWADJTAG part is unused and in its original packaging.
Return procedure for NCV59801CMTWADJTAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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