onsemi NCV8509PDW18
- Part No.:
- NCV8509PDW18
- Manufacturer:
- onsemi
- Package:
- 16-SOIC (0.295", 7.50mm Width) Exposed Pad
- Datasheet:
-
NCV8509PDW18.pdf
- Description:
- IC REG LINEAR 3.3V/1.8V 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,030
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCV8509PDW18 from onsemi is an automotive-grade dual linear voltage regulator with sequenced power-up for microcontroller core (1.8 V) and I/O (3.3 V) rails, delivering 115 mA and 100 mA respectively at ±2% output accuracy, featuring programmable slew rate, dual-drive RESET, and integrated power shunt for thermal optimization in engine control units and telematics modules.
For engineers reviewing the NCV8509PDW18 datasheet, pinout, applications, or equivalent options, key selection criteria include its 3.3 V/1.8 V dual-output sequencing, 175 µA quiescent current at light load, SOW-16 exposed-pad thermal performance, AEC-Q100 qualification, and RESET validity down to 0 V on either VIN1 or VOUT1.
Technical Context
The NCV8509PDW18 implements independent error amplifiers and bandgap references for each output, enabling precise tracking and independent regulation of VOUT1 (3.3 V) and VOUT2 (1.8 V). Its power shunt architecture routes part of VOUT2 current through external REX to reduce on-die dissipation, especially critical under high VIN1 conditions.
SLEW pin controls rise time via a 6.0 µA internal current source charging CSLEW; Delay pin provides programmable reset delay using the same principle. RESET is driven by both VIN1 and VOUT1, ensuring valid assertion even during deep brown-out events on either rail.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT1 | 3.3 V ±2% (115 mA max), powers MCU I/O rail with tight regulation across −40°C to +125°C |
| VOUT2 | 1.8 V ±2% (100 mA max), powers MCU core rail with output tracking delta ≤2.8 V relative to VOUT1 |
| Quiescent Current | 175 µA typical at 12 V VIN1 and 100 µA load, enables low-power sleep mode in automotive ECUs |
| SLEW Rate Control | Programmable via CSLEW capacitor; 469 V/s typical for VOUT1 with 33 nF (3.3 V option) |
| RESET Threshold | 96.5% of VOUT1 (typ), with 66 mV hysteresis, valid down to 0 V on VIN1 or VOUT1 due to dual-drive architecture |
| Thermal Shutdown | 150°C to 210°C trip range (guaranteed by design), protects against sustained overload in enclosed modules |
| Package | SOW-16 exposed pad (Case 751AG), RθJA = 57°C/W, RθJC = 16°C/W for PCB-level thermal management |
Pinout & Package
SOW-16 wide-body SOIC package with exposed thermal pad (Case 751AG), 10.3 mm × 7.5 mm footprint, 1.6 mm height, Pb-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SLEW (Pin 1) | Slew rate control input | Charged by 6.0 µA internal current source; sets VOUT1/VOUT2 rise time during power-up via external capacitor |
| Delay (Pin 2) | Reset delay timing input | Charged/discharged to generate programmable RESET assertion delay; latched on regulation violation |
| GND (Pin 3) | Power ground reference | Common return path for both regulators and internal circuitry; connects to exposed pad for thermal conduction |
| NC (Pins 4,5,7–9,11,14,16) | No connection | Internally unconnected; must be left floating or tied to GND per layout best practice |
| RESET (Pin 6) | Active-low reset output | Dual-drive output powered by VIN1 or VOUT1; remains valid down to 0 V on either supply |
| VOUT2 (Pin 10) | Core voltage output | 1.8 V ±2%, 100 mA regulated output for MCU core logic; supports power-shunt operation via VIN2 |
| VIN2 (Pin 12) | Secondary input for VOUT2 | Accepts shunted current from VIN1 via external REX resistor to reduce on-die power dissipation |
| VIN1 (Pin 13) | Main input for VOUT1 and bias | 6.0–18 V input; powers VOUT1, internal circuitry, and supplies RESET drive when VOUT1 fails |
| VOUT1 (Pin 15) | I/O voltage output | 3.3 V ±2%, 115 mA regulated output for MCU I/O; includes soft-start and fault recovery slew control |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced Power-Up | Ensures VOUT1 (I/O) powers before VOUT2 (core) to prevent I/O latch-up in modern MCUs |
| Power Shunt Architecture | Offloads VOUT2 current via external REX to reduce die temperature-critical for 100 mA loads at high VIN1 |
| Dual-Drive RESET | Maintains valid reset signal even if either VIN1 or VOUT1 collapses to 0 V, improving system reliability |
| Programmable SLEW Rate | Adjusts output ramp time independently for VOUT1 and VOUT2 using one external capacitor (CSLEW) |
| AEC-Q100 Qualified | Validated for automotive applications including powertrain and telematics with PPAP capability |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) Camera Module |
|---|---|
Use Scenario: Powers 32-bit MCU (e.g., S32K144) requiring separate 3.3 V I/O and 1.8 V core rails with strict power sequencing and low quiescent current during sleep. IC Role / Device Role / Timing Role: Dual linear regulator providing sequenced, low-noise, AEC-Q100-compliant power with RESET assertion during cold-crank (4.5 V VIN). Use Value: Prevents I/O latch-up during startup; power shunt reduces thermal stress at 14 V battery with 100 mA core load. | Use Scenario: Supplies image sensor and ISP in rear-view camera module operating in ambient temperatures from −40°C to +105°C. IC Role / Device Role / Timing Role: Regulates 3.3 V I/O and 1.8 V core with <2.8 V tracking delta and 175 µA IQ to meet ASIL-B power budget constraints. Use Value: Dual-drive RESET ensures reliable boot after ignition cycle; SLEW control prevents EMI during power-on. |
| Automotive Telematics Control Unit (TCU) | Electric Vehicle Battery Management System (BMS) Interface |
Use Scenario: Powers LTE modem and microcontroller in connected car TCU where thermal headroom is limited in sealed enclosure. IC Role / Device Role / Timing Role: Dual-output LDO with exposed-pad thermal path and programmable delay for safe modem initialization sequence. Use Value: Power shunt lowers junction temperature by >25°C vs. single-input regulator at 12 V/100 mA, extending lifetime. | Use Scenario: Supplies isolated communication interface (CAN transceiver + SPI isolator) in BMS slave node with stringent ESD immunity. IC Role / Device Role / Timing Role: Provides 3.3 V/1.8 V rails with 4 kV HBM ESD rating and RESET monitoring of both outputs. Use Value: RESET validity down to 0 V prevents spurious resets during battery disconnect; ±2% accuracy maintains CAN timing margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-sequenced LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NCV8509PDW25R2G | 5 V/2.5 V fixed outputs; identical pinout, package, and features | Targets MCUs requiring 5 V I/O (e.g., legacy 8051-based modules); not suitable for 3.3 V/1.8 V systems | Select only if system requires 5 V I/O rail; otherwise incompatible due to non-adjustable outputs. |
| TPS74901RGWR | Single 3.3 V output (300 mA), no VOUT2 or power shunt; 20-pin QFN vs. 16-pin SOW | Lacks core-rail regulation and sequencing; requires second regulator for 1.8 V, increasing BOM and layout complexity | Use only for simplified 3.3 V-only designs; cannot replace NCV8509PDW18 in dual-rail applications. |
Compared with NCV8509PDW25R2G, the NCV8509PDW18 delivers optimized 3.3 V/1.8 V sequencing for modern ARM Cortex-M MCUs, while TPS74901RGWR lacks core-rail support and thermal shunting-making it unsuitable as a drop-in replacement.
Availability
NCV8509PDW18 is available at Aetrix Electronics and suitable for automotive powertrain control, telematics modules, and ADAS camera systems requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.
Supply support for NCV8509PDW18 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensors, and connectivity solutions for automotive, industrial, and cloud infrastructure markets.
The NCV8509PDW18 belongs to the NCV8509 Series of sequenced dual LDOs designed specifically for automotive microcontroller power domains, emphasizing robustness, thermal efficiency, and fail-safe reset behavior in harsh environments.
FAQ
What is the output voltage configuration of the NCV8509PDW18?
The NCV8509PDW18 is factory-configured for 3.3 V ±2% on VOUT1 (115 mA max) and 1.8 V ±2% on VOUT2 (100 mA max). These values are fixed and non-adjustable; the "18" suffix in the part number explicitly denotes the 3.3 V/1.8 V variant per onsemi's marking diagram and ordering information.
Does the NCV8509PDW18 support power sequencing between its two outputs?
Yes, the NCV8509PDW18 implements inherent power-up sequencing where VOUT1 (3.3 V I/O rail) powers up before VOUT2 (1.8 V core rail). This prevents I/O latch-up in modern microcontrollers and is achieved through internal biasing and error amplifier timing-no external components are required to enable this behavior in the NCV8509PDW18.
How does the power shunt function work on the NCV8509PDW18?
The NCV8509PDW18 uses VIN2 and an external REX resistor to route part of the VOUT2 current off-chip. When VIN1 exceeds ~4.5 V, the internal shunt activates, reducing on-die power dissipation. For a 100 mA VOUT2 load at 12 V VIN1, this can lower junction temperature by over 25°C compared to a conventional dual-LDO without shunt capability.
What is the minimum operating input voltage for the NCV8509PDW18?
The NCV8509PDW18 requires a minimum input voltage of 6.0 V on VIN1 to maintain regulation across its full temperature range (−40°C to +125°C). Below 6.0 V, VOUT1 and VOUT2 may drop out of specification; VIN1 absolute maximum is 50 V DC, with peak transient rating also at 50 V per the datasheet's Maximum Ratings table.
Is the NCV8509PDW18 pin-compatible with other variants in the NCV8509 series?
Yes, all NCV8509 variants-including NCV8509PDW18, NCV8509PDW25R2G, and NCV8509PDW26R2G-share identical SOW-16 exposed-pad packaging and pinout. The only differences are factory-set output voltages; no PCB redesign is needed when migrating between variants, provided the new voltage pair meets system requirements.
NCV8509PDW18 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 50V
- Voltage - Output (Min/Fixed):
- 3.3V, 1.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.6V @ 100mA, -
- Current - Output:
- 115mA, 100mA
- Current - Quiescent (Iq):
- 175 µA
- Current - Supply (Max):
- 10 mA
- PSRR:
- -
- Control Features:
- Reset
- Protection Features:
- Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
NCV8509PDW18 FAQ
1.How can I place an order for NCV8509PDW18 through Aetrix?
Please submit a Request for Quotation (RFQ) for NCV8509PDW18 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCV8509PDW18 reliable?
The price and inventory of NCV8509PDW18 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCV8509PDW18 is usually 5 days.
3.What payment methods are accepted for NCV8509PDW18?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCV8509PDW18 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCV8509PDW18?
NCV8509PDW18 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCV8509PDW18 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCV8509PDW18?
For technical support, including NCV8509PDW18 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCV8509PDW18 requirements.
6.How does Aetrix verify that NCV8509PDW18 is sourced from the original manufacturer or authorized distributors?
All NCV8509PDW18 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCV8509PDW18 meets industry standards.
7.What is the process for return or replacement of NCV8509PDW18?
All NCV8509PDW18 units undergo pre-shipment inspection (PSI). If there is an issue with NCV8509PDW18, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCV8509PDW18 part is unused and in its original packaging.
Return procedure for NCV8509PDW18:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCV8509PDW18 Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

