onsemi NCV8509PDW25G

Overview

NCV8509PDW25G from onsemi is an automotive-grade dual linear voltage regulator with sequenced power-up, delivering 5 V ±2% @ 115 mA (VOUT1) and 2.5 V ±2% @ 100 mA (VOUT2) to protect microcontroller I/O and core logic during startup. It features programmable slew rate control, dual-drive RESET with 0 V validity, thermal shutdown, and power shunt functionality for optimized on-chip dissipation in powertrain and telematics systems.

For engineers reviewing the NCV8509PDW25G datasheet, pinout, applications, or equivalent options, key selection criteria include output sequencing integrity, RESET threshold hysteresis (25 mV typ), SLEW-controlled rise time (370 V/s for VOUT2), power shunt compatibility with external REX, and AEC-Q100 qualification for automotive deployment.

Technical Context

The NCV8509PDW25G implements independent error amplifiers and bandgap references for each output, enabling precise tracking and independent load regulation. Its dual-drive RESET circuit draws power from both VIN1 and VOUT1, ensuring reset validity down to 0 V on either rail - a critical feature for fail-safe microcontroller initialization.

Power shunt operation uses internal NPN transistor Q1 and external resistor REX to divert VOUT2 current path, reducing on-die power dissipation by shifting heat off-chip. SLEW pin controls VOUT1/VOUT2 ramp rates via external capacitor (e.g., 33 nF yields 370 V/s for 2.5 V output), while Delay pin sets RESET timeout using programmable charge current (6.0 µA typ).

Key Specifications

Pinout & Package

NCV8509PDW25G uses a 16-pin SOIC wide-body package with exposed thermal pad (Case 751AG), optimized for automotive PCB layouts requiring robust thermal performance and AEC-Q100 compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-sequenced LDO regulator applications.

Compared with NCV8509PDW25G, the 2.6 V variant maintains identical sequencing and RESET behavior but shifts core rail voltage upward, while the 3.3 V/1.8 V variant trades I/O compatibility for lower thermal load - all three share AEC-Q100 qualification, power shunt capability, and SLEW/Reset programmability.

Availability

NCV8509PDW25G is available at Aetrix Electronics and suitable for automotive powertrain control units, telematics gateways, and ADAS camera modules requiring stable component supply, AEC-Q100 compliance, and long-term lifecycle support.

Supply support for NCV8509PDW25G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient, high-reliability components for automotive, industrial, and cloud power applications.

The NCV8509PDW25G belongs to the NCV8509 Series of sequenced dual LDOs, designed specifically for automotive microcontroller power sequencing with integrated RESET, slew control, and power shunt to meet stringent ASIL-B functional safety requirements.

FAQ

What is the guaranteed minimum RESET threshold voltage for NCV8509PDW25G?

The guaranteed minimum RESET threshold voltage for NCV8509PDW25G is 94.5% of VOUT1, which equals 4.725 V (since VOUT1 = 5.0 V nominal). This threshold applies during rising VOUT1 and is validated across −40 °C to +125 °C junction temperature. The device also provides hysteresis (25–50 mV) to prevent chatter during marginal conditions, and the dual-drive architecture ensures RESET remains valid even if VOUT1 falls to 0 V after initial assertion.

How does the power shunt function work in NCV8509PDW25G, and what resistor value should be used for REX?

The power shunt in NCV8509PDW25G routes part of the VOUT2 current path through external resistor REX connected between VIN1 and VIN2, reducing on-die power dissipation. For the 5 V/2.5 V variant, the recommended REX value is 138 Ω - derived from (VIN(max) − 4.5 V)/IOUT2(max) = (18 V − 4.5 V)/100 mA. Using this value shifts ~1.07 W off-chip at full load, lowering junction temperature by up to 22 °C compared to non-shunt operation.

Can NCV8509PDW25G operate with input voltage below 6 V, and what is the minimum functional VIN1?

NCV8509PDW25G is specified for 6.0 V ≤ VIN1 ≤ 18 V in electrical characteristics, but absolute maximum ratings allow VIN1 down to −0.3 V (with transient tolerance to 50 V). Operation below 6 V is not characterized: VOUT1 dropout is 400 mV at 100 mA, so minimum functional VIN1 ≈ 5.4 V to sustain 5.0 V output. Below that, regulation degrades; thermal and RESET behavior remain valid, but output accuracy and load capability are not guaranteed per datasheet.

What is the purpose of the NC pins on NCV8509PDW25G, and how should they be handled on the PCB?

The NC pins (4, 5, 7–9, 11, 14, 16) on NCV8509PDW25G are internally unconnected and must remain electrically floating - no routing, stitching, or grounding is permitted. Per onsemi layout guidance, these pins may be left unmasked or covered with solder mask, but must not be tied to GND, VOUT, or any other net. Doing so risks internal leakage paths or ESD susceptibility, and violates AEC-Q100 board-level validation requirements for automotive use.

Does NCV8509PDW25G support output voltage tracking, and what is the maximum allowable delta between VOUT1 and VOUT2?

Yes, NCV8509PDW25G supports output voltage tracking: Delta 1 [VOUT1 − VOUT2] is guaranteed ≤3.2 V, and Delta 2 [VOUT2 − VOUT1] is guaranteed ≤100 mV under matched output capacitance (COUT1 = COUT2) and equal load currents (IOUT1 = IOUT2). This tight tracking ensures safe power sequencing for MCUs where core voltage must never exceed I/O voltage during startup or transient events - critical for preventing latch-up in mixed-voltage SoCs.