onsemi NCV8509PDW26G
- Part No.:
- NCV8509PDW26G
- Manufacturer:
- onsemi
- Package:
- 16-SOIC (0.295", 7.50mm Width) Exposed Pad
- Datasheet:
-
NCV8509PDW26G.pdf
- Description:
- IC REG LINEAR 5V/2.6V 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,447
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NCV8509PDW26G from onsemi is an automotive-grade dual linear voltage regulator with sequenced power-up, delivering 5.0 V ±2% @ 115 mA (VOUT1) and 2.6 V ±2% @ 100 mA (VOUT2) to protect microcontroller I/O and core logic during startup. It features programmable slew rate control, dual-drive RESET with 0 V validity, thermal shutdown, and integrated power shunt for optimized on-chip dissipation. Used in automotive powertrain and telematics systems requiring AEC-Q100 compliance.
For engineers reviewing the NCV8509PDW26G datasheet, pinout, applications, or equivalent options, key selection criteria include output sequencing integrity, RESET threshold hysteresis (50–150 mV), SLEW-controlled rise time (710 V/s typical for 5 V/2.6 V variant), power shunt enablement via REX, and SOIC-16 exposed-pad thermal performance (RθJA = 57 °C/W).
Technical Context
The NCV8509PDW26G implements independent error amplifiers and bandgap references for each output, enabling precise tracking and independent regulation of VOUT1 (5 V) and VOUT2 (2.6 V). Its dual-drive RESET circuit derives power from both VIN1 and VOUT1, ensuring reset validity down to 0 V on either rail - a critical feature for fail-safe automotive microcontroller boot sequences.
Power sequencing is enforced via internal SLEW pin control (6.0 µA charging current) and external CSLEW capacitor (e.g., 33 nF), generating a linear ramp that gates output enablement until VOUT1 reaches regulation. The power shunt architecture routes part of VOUT2 current through VIN2 using external REX (e.g., 138 Ω), reducing on-die power dissipation by up to 1.07 W at 18 V input and 100 mA load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT1 | 5.0 V ±2% (4.9–5.1 V); powers MCU I/O rails with tight tolerance for interface compatibility. |
| VOUT2 | 2.6 V ±2% (2.548–2.652 V); supplies MCU core logic with low-noise, stable bias. |
| Output Current | VOUT1: 115 mA max; VOUT2: 100 mA max - supports dual-rail SoC power without external boost. |
| Quiescent Current | 175 µA typical at light load; enables ultra-low standby power in always-on automotive modules. |
| SLEW Rate (VOUT1) | 710 V/s typical with 33 nF capacitor; ensures controlled, ESD-safe power-up ramp for I/O structures. |
| RESET Threshold | 96.5% of VOUT1 (4.73 V typ); with 50–150 mV hysteresis - prevents chatter during brownout recovery. |
| Thermal Shutdown | 150–210 °C junction range; latches both outputs off to prevent thermal runaway in enclosed ECUs. |
Pinout & Package
NCV8509PDW26G uses a 16-lead SOIC wide-body package with exposed thermal pad (Case 751AG, PDW suffix), measuring 10.3 mm × 7.5 mm × 2.5 mm, optimized for automotive PCB layouts requiring high thermal reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SLEW (Pin 1) | Soft-start timing control | Charged at 6.0 µA to set VOUT1/VOUT2 rise time; connects to 33 nF capacitor to GND. |
| Delay (Pin 2) | RESET delay timing | Sources 6.0 µA to external CDelay capacitor; determines RESET assertion delay after regulation. |
| GND (Pin 3) | Power ground reference | Common return for both regulators and internal circuitry; tied to exposed pad for thermal conduction. |
| NC (Pins 4,5,7–9,11,14,16) | No connection | Internally unconnected; must remain floating or grounded per layout guidelines - no routing required. |
| RESET (Pin 6) | Active-low system reset | Dual-supplied (VIN1 + VOUT1); valid down to 0 V on either rail; drives open-drain with 1 mA sink capability. |
| VOUT2 (Pin 10) | Core voltage output | 2.6 V ±2%, 100 mA regulated supply for MCU core; requires 10 µF ceramic output capacitor. |
| VIN2 (Pin 12) | Shunt input for VOUT2 | Accepts current routed via external REX resistor; reduces on-die power dissipation when used with VIN1. |
| VIN1 (Pin 13) | Main input for VOUT1 & bias | 6–18 V DC input; powers VOUT1, internal bias, and RESET drive; withstands 50 V transients. |
| VOUT1 (Pin 15) | I/O voltage output | 5.0 V ±2%, 115 mA regulated supply for MCU I/O; tracks VOUT2 within 3.2 V delta under matched loads. |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced Power-Up | Guarantees VOUT1 rises before VOUT2 with controlled slew, preventing I/O latch-up during MCU boot. |
| Dual-Drive RESET | Remains valid even if VOUT1 collapses to 0 V (powered by VIN1) or VIN1 drops to 0 V (powered by VOUT1). |
| Programmable SLEW Rate | Adjustable rise time via external capacitor (e.g., 33 nF → 710 V/s for 5 V output), eliminating need for external soft-start ICs. |
| Integrated Power Shunt | Offloads VOUT2 current via REX to VIN2, reducing on-chip dissipation by >1 W at high VIN - extends thermal margin in compact ECUs. |
| AEC-Q100 Qualified | Qualified to Grade 1 (−40 °C to +125 °C ambient), PPAP-capable, with change-controlled NCV prefix for automotive traceability. |
Applications
| Automotive Powertrain Control Unit | Telematics Gateway Module |
|---|---|
Use Scenario: Engine control unit (ECU) powering 32-bit MCU with separate 5 V I/O and 2.6 V core rails under cold-crank (6 V) and load-dump (50 V) conditions. IC Role / Device Role / Timing Role: Dual linear regulator providing sequenced, fault-tolerant power with RESET assertion during undervoltage events. Use Value: Prevents MCU lockup during battery transients; eliminates need for discrete reset supervisor and external sequencing logic. | Use Scenario: Cellular/V2X telematics module requiring simultaneous 5 V (CAN transceiver, USB PHY) and 2.6 V (application processor core) supplies with low quiescent current. IC Role / Device Role / Timing Role: Primary power management IC enabling fast, reliable boot sequence and brownout-safe reset signaling. Use Value: Reduces BOM count by integrating dual regulation, RESET, slew control, and power shunt in one AEC-Q100 package. |
| ADAS Camera ECU | Body Control Module (BCM) |
Use Scenario: Front-facing camera ECU supplying image sensor interface (5 V) and ISP core (2.6 V) while meeting ASIL-B functional safety requirements. IC Role / Device Role / Timing Role: Safety-relevant power sequencer ensuring deterministic power-up order and fail-safe reset generation. Use Value: Supports diagnostic coverage for ISO 26262 via dual-supply RESET validity and thermal shutdown latching. | Use Scenario: Central body controller managing door modules, lighting, and HVAC with always-on 5 V and periodic 2.6 V wake-up domains. IC Role / Device Role / Timing Role: Low-quiescent dual regulator enabling <100 µA sleep current while maintaining fast wake-up response. Use Value: Extends vehicle battery life in parked state without compromising boot-time responsiveness. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-sequenced linear regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NCV8509PDW25G | Same package and pinout; delivers 5 V/2.5 V instead of 5 V/2.6 V; identical quiescent current, slew, and RESET specs. | Used where MCU core requires 2.5 V (e.g., certain Infineon AURIX variants); not suitable for 2.6 V–specified SoCs. | Select NCV8509PDW25G only when target MCU datasheet explicitly specifies 2.5 V core voltage. |
| NCV8509PDW18G | Same footprint; provides 3.3 V/1.8 V outputs; lower dropout and different VOUT tracking behavior (Delta 1 = 2.8 V). | Targeted at lower-voltage MCUs (e.g., ARM Cortex-M7 cores); incompatible with 5 V I/O interfaces due to VOUT1 mismatch. | Choose NCV8509PDW18G for next-gen low-power automotive MCUs requiring 3.3 V I/O and 1.8 V core - not a drop-in replacement for NCV8509PDW26G. |
Compared with NCV8509PDW25G and NCV8509PDW18G, the NCV8509PDW26G uniquely supports 2.6 V core rails common in legacy automotive MCUs (e.g., Freescale MPC56xx), offers highest VOUT1–VOUT2 tracking delta (3.2 V), and maintains full AEC-Q100 qualification across its specified operating range.
Availability
NCV8509PDW26G is available at Aetrix Electronics and suitable for automotive powertrain control units, telematics gateways, and ADAS camera ECUs requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for NCV8509PDW26G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, with leadership in automotive, industrial, cloud, and IoT power management solutions.
The NCV8509 Series belongs to onsemi's automotive analog power portfolio, designed specifically for dual-rail microcontroller power sequencing in harsh-temperature, high-reliability environments such as engine control and vehicle connectivity systems.
FAQ
What is the exact output voltage tolerance for both rails of the NCV8509PDW26G?
The NCV8509PDW26G delivers VOUT1 = 5.0 V with ±2% tolerance (4.9–5.1 V) and VOUT2 = 2.6 V with ±2% tolerance (2.548–2.652 V), measured across −40 °C to +125 °C junction temperature and 1–100 mA load range. These tolerances are guaranteed in production test and documented in the Electrical Characteristics table on page 2 of the datasheet.
How does the power shunt function work in the NCV8509PDW26G, and what resistor value is recommended?
The NCV8509PDW26G power shunt routes part of the VOUT2 current through VIN2 using an external REX resistor. For the 5 V/2.6 V variant, a 138 Ω resistor is recommended (as shown in Figure 1), enabling up to 1.07 W power reduction on-die at 18 V input and 100 mA load. REX must be placed between VIN1 and VIN2 pins.
Can the NCV8509PDW26G generate a valid RESET signal even if VOUT1 drops to 0 V?
Yes. The NCV8509PDW26G features dual-drive RESET, meaning the RESET output remains active and valid even when VOUT1 collapses to 0 V - because it draws operating power from VIN1 during that condition. Similarly, RESET stays valid if VIN1 falls to 0 V, powered by VOUT1. This ensures fail-safe reset assertion in all fault scenarios.
What is the thermal resistance (RθJA) of the NCV8509PDW26G in its SOIC-16 exposed-pad package?
The NCV8509PDW26G in the PDW (SOIC-16 wide-body exposed pad) package has a maximum junction-to-ambient thermal resistance (RθJA) of 57 °C/W, measured on standard JEDEC 2-layer board with 2 oz copper. With adequate PCB copper area (≥600 mm²), RθJA can be reduced to ~60 °C/W, supporting continuous operation at full load up to +105 °C ambient.
Is the NCV8509PDW26G pin-compatible with other variants in the NCV8509 family?
Yes. All NCV8509 variants - including NCV8509PDW26G, NCV8509PDW25G, and NCV8509PDW18G - share identical SOIC-16 PDW pinout, package dimensions, and thermal pad layout. Output voltage differences are encoded in the part number suffix (26/25/18) and do not affect PCB footprint or interconnect design.
NCV8509PDW26G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 50V
- Voltage - Output (Min/Fixed):
- 5V, 2.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.6V @ 100mA, -
- Current - Output:
- 115mA, 100mA
- Current - Quiescent (Iq):
- 175 µA
- Current - Supply (Max):
- 10 mA
- PSRR:
- -
- Control Features:
- Reset
- Protection Features:
- Over Temperature
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
NCV8509PDW26G FAQ
1.How can I place an order for NCV8509PDW26G through Aetrix?
Please submit a Request for Quotation (RFQ) for NCV8509PDW26G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NCV8509PDW26G reliable?
The price and inventory of NCV8509PDW26G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NCV8509PDW26G is usually 5 days.
3.What payment methods are accepted for NCV8509PDW26G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NCV8509PDW26G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NCV8509PDW26G?
NCV8509PDW26G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NCV8509PDW26G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NCV8509PDW26G?
For technical support, including NCV8509PDW26G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NCV8509PDW26G requirements.
6.How does Aetrix verify that NCV8509PDW26G is sourced from the original manufacturer or authorized distributors?
All NCV8509PDW26G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NCV8509PDW26G meets industry standards.
7.What is the process for return or replacement of NCV8509PDW26G?
All NCV8509PDW26G units undergo pre-shipment inspection (PSI). If there is an issue with NCV8509PDW26G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NCV8509PDW26G part is unused and in its original packaging.
Return procedure for NCV8509PDW26G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NCV8509PDW26G Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

