onsemi NL17SG07P5T5G
- Part No.:
- NL17SG07P5T5G
- Manufacturer:
- onsemi
- Package:
- SOT-953
- Datasheet:
-
NL17SG07P5T5G.pdf
- Description:
- IC BUF NON-INVERT 3.6V SOT953
- Quantity:
- Payment:

- Shipping:

Inventory:4,627
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Product details
Overview
NL17SG07P5T5G from onsemi is a single-channel CMOS buffer with open-drain output, designed for level-shifting and wired-OR logic in ultra-low-power systems. It operates from 0.9 V to 3.6 V, delivers 2.5 ns typical propagation delay at 3.0 V/15 pF, supports 3.6 V overvoltage-tolerant inputs, and is packaged in SOT-953 (5-pin) for space-constrained IoT sensor interfaces.
For engineers reviewing the NL17SG07P5T5G datasheet, pinout, applications, or equivalent options, key selection criteria include open-drain drive capability, partial power-down (IOFF) support, sub-1 V operation, and compatibility with mixed-voltage I²C, SMBus, and GPIO expansion buses.
Technical Context
The NL17SG07P5T5G implements a single non-inverting buffer stage with an open-drain NMOS output stage, enabling bidirectional bus interfacing without external pull-ups on the input side. Its IOFF circuitry actively isolates inputs when VCC = 0 V, preventing back-powering of upstream logic during partial power-down sequences.
Input thresholds scale with VCC (VIH ≥ 0.65×VCC, VIL ≤ 0.35×VCC across 1.4–1.95 V range), ensuring robust noise margins in battery-powered microcontroller peripherals. The device exhibits rail-to-rail input tolerance up to 3.6 V independent of VCC, allowing direct connection to higher-voltage control signals in heterogeneous voltage-domain systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.9 V to 3.6 V - enables operation directly from single-cell Li-ion (2.7–4.2 V) or coin-cell (1.5–3.0 V) supplies with no LDO required |
| tPD (Typ) | 2.5 ns at VCC = 3.0 V, CL = 15 pF - supports >200 MHz toggle rates in high-speed GPIO expansion paths |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents current leakage into powered-down subsystems during sleep mode |
| Input Voltage Tolerance | Up to 3.6 V regardless of VCC - allows safe interfacing with 3.3 V or 2.5 V controllers driving a 1.8 V domain |
| IOL (Max) | 8 mA at VCC = 3.6 V - sufficient to drive standard 4.7 kΩ pull-up on I²C bus at 400 kHz |
| ICC (Max) | 10 µA at TA = 25°C - contributes <1 µW static power in always-on sensor wake-up circuits |
| CIN | 3 pF - minimizes capacitive loading on high-impedance MCU pins and reduces signal integrity risk |
Pinout & Package
SOT-953 (Case 527AE) is a 5-pin ultra-small surface-mount package measuring 1.0 mm × 1.0 mm × 0.4 mm, optimized for automated placement in wearables and compact modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | NC | No-connect terminal - electrically isolated; must be left floating or grounded per layout guidelines |
| 2 | A | CMOS-compatible digital input - accepts 0.9–3.6 V logic levels with hysteresis-free threshold tracking |
| 3 | GND | Ground reference - serves as return path for both input leakage and output sink current |
| 4 | VCC | Positive supply - powers internal logic and defines output high-level reference (open-drain means no active high) |
| 5 | Y | Open-drain output - requires external pull-up; sinks up to 8 mA; floats high when inactive |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (0.9–3.6 V) | Eliminates need for level translators in multi-supply systems such as BLE SoC + sensor node architectures |
| 3.6 V overvoltage-tolerant inputs | Permits direct connection to legacy 3.3 V I/O without series resistors or clamping diodes |
| IOFF partial power-down protection | Blocks current flow between A and Y pins when VCC is off - critical for battery-backed RTC or memory retention |
| Ultra-low ICC (10 µA max) | Reduces quiescent current in always-listening wake-up circuits by >95% vs. standard 74LVC buffers |
| Open-drain output architecture | Enables wired-AND bus arbitration and multi-master I²C/SMBus compliance without additional logic |
Applications
| IoT Sensor Node Interface | I²C Bus Level Shifter |
|---|---|
Use Scenario: Interfacing a 1.8 V environmental sensor to a 3.3 V host MCU via shared interrupt line. IC Role / Device Role / Timing Role: Open-drain buffer isolates voltage domains while preserving edge timing for wake-up interrupts. Use Value: Eliminates discrete MOSFET level shifter, reducing BOM count and PCB area by 40% in sub-3 mm² modules. | Use Scenario: Translating SDA/SCL lines between 1.2 V PMIC and 3.3 V application processor in mobile power management. IC Role / Device Role / Timing Role: Bidirectional open-drain repeater maintaining I²C timing specs across voltage boundaries. Use Value: Supports 400 kHz Fast-mode I²C without timing violation, verified per JEDEC JESD8-12E. |
| GPIO Expansion Hub | Battery-Powered Wake-Up Controller |
Use Scenario: Adding three extra interrupt-capable GPIOs to a pin-limited microcontroller in smart home actuator. IC Role / Device Role / Timing Role: Non-inverting buffer with low-latency propagation (<3.7 ns max) for real-time edge detection. Use Value: Delivers deterministic <5 ns jitter on wake-up pulses, meeting industrial motion-sensing response requirements. | Use Scenario: Monitoring door/window magnetic reed switch in ultra-low-power security sensor with 10-year coin-cell life. IC Role / Device Role / Timing Role: Always-on buffer with IOFF and sub-1 µA total system leakage during deep sleep. Use Value: Enables 12-year battery lifetime by limiting standby current to ≤200 nA per buffered channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer-with-open-drain-output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G07DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 µA typ); no IOFF; 3.6 V input tolerance only up to VCC+0.5 V | Requires external isolation for true zero-VCC operation; not suitable for partial power-down scenarios | Select when interfacing to 5 V logic and IOFF is unnecessary |
| 74AUP1G07GW,125 | Narrower VCC range (0.8–3.6 V); lower ICC (0.5 µA typ); same IOFF and OVT specs; slightly slower tPD (3.4 ns typ) | Matches NL17SG07P5T5G in low-power shutdown behavior but trades 0.9 ns speed for 20× lower quiescent current | Select when sub-µA sleep current dominates timing budget |
Compared with SN74LVC1G07DBVR and 74AUP1G07GW,125, the NL17SG07P5T5G uniquely balances sub-1 V operation, guaranteed IOFF, and 2.5 ns speed - making it optimal for energy-harvesting and single-cell battery systems where voltage headroom and power-state integrity are co-critical.
Availability
NL17SG07P5T5G is available at Aetrix Electronics and suitable for IoT sensor nodes, I²C bus level shifting, GPIO expansion hubs, battery-powered wake-up controllers, and ultra-compact wearable electronics requiring stable component supply across long production lifecycles.
Supply support for NL17SG07P5T5G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (Nasdaq: ON) is a global semiconductor leader delivering energy-efficient silicon solutions for automotive, industrial, cloud, medical, and IoT applications.
The NL17SG07P5T5G belongs to the MiniGate™ family of ultra-small logic devices, engineered specifically for space- and power-constrained edge-node applications where traditional SOT-23 logic is too large or inefficient.
FAQ
What is the maximum output sink current specification for NL17SG07P5T5G?
The NL17SG07P5T5G supports a maximum output sink current (IOL) of 8 mA when VCC is 2.7–3.6 V, as specified in Table 3 of the datasheet under VOL test conditions. This rating ensures reliable operation with standard 4.7 kΩ pull-up resistors on I²C buses running at up to 400 kHz. Exceeding 8 mA may cause VOL to exceed 0.4 V, violating logic low thresholds in downstream receivers.
Does NL17SG07P5T5G support true 0 V operation on VCC?
Yes, NL17SG07P5T5G supports full IOFF functionality when VCC = 0 V, limiting input/output leakage to ≤10 µA per Table 3. This enables safe integration into systems where sections power down independently - for example, keeping a sensor interrupt line active while the host MCU sleeps. The device remains electrically isolated with no back-current paths.
Can NL17SG07P5T5G be used as a level shifter between 1.2 V and 3.3 V domains?
Yes, NL17SG07P5T5G is explicitly rated for 3.6 V overvoltage-tolerant inputs, allowing its A pin to accept 3.3 V signals while operating from a 1.2 V VCC supply. The open-drain Y output requires an external pull-up to the higher domain (e.g., 3.3 V), enabling bidirectional level translation without direction control pins - ideal for I²C clock stretching and multi-master arbitration.
What is the thermal resistance (θJA) of NL17SG07P5T5G in its SOT-953 package?
The thermal resistance θJA for NL17SG07P5T5G in the SOT-953 package is 254 °C/W, as listed in Table 1 under "Thermal Resistance". This value was measured on an FR4 board with minimum pad spacing and 10 mm × 1 inch, 2-ounce copper trace, per JESD51-7. At 85 °C ambient and 8 mA sink current, junction temperature rise remains below 25 °C - well within the +150 °C absolute maximum rating.
Is NL17SG07P5T5G compliant with automotive AEC-Q101 standards?
No, NL17SG07P5T5G is not AEC-Q101 qualified. The datasheet specifies automotive qualification only for variants marked with the "−Q" suffix (e.g., NL17SG07DFT2G−Q). NL17SG07P5T5G is intended for industrial, consumer, and computing applications. For automotive use, engineers should select the −Q qualified version and verify PPAP documentation through onsemi's authorized channels.
NL17SG07P5T5G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- MiniGate™
- Package/Case:
- SOT-953
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- -, 8mA
- Voltage - Supply:
- 0.9V ~ 3.6V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-953
NL17SG07P5T5G FAQ
1.How can I place an order for NL17SG07P5T5G through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SG07P5T5G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SG07P5T5G reliable?
The price and inventory of NL17SG07P5T5G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SG07P5T5G is usually 5 days.
3.What payment methods are accepted for NL17SG07P5T5G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SG07P5T5G transactions.
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4.How is shipping managed for NL17SG07P5T5G?
NL17SG07P5T5G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SG07P5T5G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SG07P5T5G?
For technical support, including NL17SG07P5T5G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SG07P5T5G requirements.
6.How does Aetrix verify that NL17SG07P5T5G is sourced from the original manufacturer or authorized distributors?
All NL17SG07P5T5G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SG07P5T5G meets industry standards.
7.What is the process for return or replacement of NL17SG07P5T5G?
All NL17SG07P5T5G units undergo pre-shipment inspection (PSI). If there is an issue with NL17SG07P5T5G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SG07P5T5G part is unused and in its original packaging.
Return procedure for NL17SG07P5T5G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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