onsemi NL17SH08P5T5G
- Part No.:
- NL17SH08P5T5G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- SOT-953
- Datasheet:
-
NL17SH08P5T5G.pdf
- Description:
- IC GATE AND 1CH 2-INP SOT953
- Quantity:
- Payment:

- Shipping:

Inventory:4,980
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Product details
Overview
NL17SH08P5T5G from onsemi is a single 2-input AND gate in SOT-953 package, fabricated using advanced high-speed CMOS silicon-gate technology. It delivers 3.5 ns typical propagation delay at 5.0 V, supports 2.0–5.5 V supply operation, and features 7.0 V input tolerance for mixed-voltage interfacing (e.g., 5 V to 3 V logic translation) in industrial control modules.
For engineers reviewing the NL17SH08P5T5G datasheet, pinout, applications, or equivalent options, key selection criteria include propagation delay vs. supply voltage, input overvoltage robustness, output drive capability at 4 mA/8 mA, and SOT-953 footprint compatibility with space-constrained PCB layouts.
Technical Context
The NL17SH08P5T5G implements a buffered CMOS AND gate with multi-stage internal circuitry, delivering balanced tPLH/tPHL delays and high noise immunity. Its input structure withstands up to 7.0 V regardless of VCC, enabling safe level-shifting between 3.0 V and 5.0 V domains without external clamping.
It operates across −55°C to +125°C, meets Level 1 moisture sensitivity, and complies with Pb-free requirements. The device exhibits low quiescent ICC (≤1.0 µA max at 25°C) and supports dynamic loads up to 50 pF while maintaining sub-10 ns delay at 5.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 5.5 V - Enables direct use in both 3.3 V and 5.0 V systems without level shifters. |
| tPD (Typ) | 3.5 ns at VCC = 5.0 V, CL = 15 pF - Supports >100 MHz toggle rates in timing-critical combinational logic paths. |
| Input Voltage Range | −0.5 V to 7.0 V - Allows safe interfacing of 5 V inputs to 3 V supplies without damage or external protection. |
| IOL / IOH | ±25 mA DC output drive - Sustains fan-out to ≥10 standard CMOS loads at 3.3 V or 5 V. |
| VIH / VIL | VIH = 3.85 V (min), VIL = 1.65 V (max) at VCC = 5.5 V - Ensures robust noise margins (>0.8 V) under worst-case conditions. |
| ICC (Max) | 1.0 µA at TA = 25°C - Minimizes static power in battery-backed or always-on subsystems. |
Pinout & Package
SOT-953 (1.00 × 0.80 × 0.37 mm, 0.35 mm pitch) - ultra-compact 5-pin surface-mount package with exposed pad not present; suitable for high-density routing and reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN B | Second logic input; accepts 0–7.0 V signals independent of VCC; enables mixed-voltage AND logic. |
| 2 | IN A | Primary logic input; electrically identical to Pin 1; dual-input symmetry simplifies layout routing. |
| 3 | GND | Ground reference for all I/O and internal circuitry; must be low-impedance for stable noise immunity. |
| 4 | VCC | Positive supply rail; powers internal buffer and output stage; decoupling capacitor required within 2 mm. |
| 5 | OUT Y | CMOS-compatible AND output; drives high/low states with rail-to-rail swing and 4 mA/8 mA sink/source capability. |
Key Features
| Feature | Design Value |
|---|---|
| High-speed propagation | 3.5 ns typical delay at 5.0 V enables use in clock distribution, address decoding, and fast enable gating. |
| Input overvoltage tolerance | 7.0 V absolute max input rating allows direct connection to 5 V buses while powered from 3.3 V - eliminates level translators. |
| Power-down input protection | Inputs remain protected during VCC = 0 V; prevents back-powering or latch-up when system rails sequence asymmetrically. |
| Pb-free SOT-953 package | RoHS-compliant 1.00 mm × 0.80 mm footprint reduces board area by >60% vs. SOIC-5 and supports automated optical inspection. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
Use Scenario: Combining enable signals from multiple proximity sensors before triggering a microcontroller interrupt. IC Role / Device Role / Timing Role: Single-point AND gate performing synchronous signal validation prior to MCU wake-up. Use Value: Eliminates need for firmware polling; reduces system current by keeping MCU in deep sleep until all conditions are met. | Use Scenario: Gating headlight activation only when both ignition ON and ambient light sensor indicates darkness. IC Role / Device Role / Timing Role: Hardware-level safety interlock ensuring dual-condition validation before power delivery. Use Value: Prevents accidental activation due to single-sensor fault; meets ASIL-A functional safety intent without software overhead. |
| Portable Medical Device Logic | Smart Energy Meter Communication |
Use Scenario: Enabling SPI chip select only when both power-good and reset-release signals are asserted. IC Role / Device Role / Timing Role: Glue logic synchronizing power sequencing and peripheral initialization in battery-powered diagnostics units. Use Value: Guarantees zero current draw from unpowered peripherals; extends battery life by preventing partial initialization states. | Use Scenario: Validating simultaneous presence of PLC modem ready and meter firmware handshake signals before data transmission. IC Role / Device Role / Timing Role: Hardware arbitration gate ensuring communication channel readiness before packet transmission. Use Value: Reduces RF collision and retry overhead by eliminating transmission attempts during modem setup phase. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input AND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G08DBVR | Higher ICC (10 µA max), same SOT-23-5 package, 1.65–5.5 V VCC range, 3.7 ns tPD at 3.3 V. | LVC family offers tighter VOH/VOL specs but lacks 7.0 V input tolerance; requires external clamping for 5 V inputs. | Select when operating strictly within 1.8–3.3 V domains and higher drive strength (32 mA) is needed. |
| 74AUP1G08GW,125 | Ultra-low ICC (0.9 µA typ), 0.8–3.6 V VCC, 5.1 ns tPD at 3.0 V, smaller XSON-6 package (1.2 × 1.0 mm). | AUP family optimized for sub-1 V logic; incompatible with 5 V inputs or outputs; no overvoltage protection. | Select for battery-powered IoT nodes where <1 µA quiescent current and 1.8 V operation are mandatory. |
Compared with SN74LVC1G08DBVR and 74AUP1G08GW,125, the NL17SH08P5T5G uniquely supports 5 V-tolerant inputs at 3.3 V supply - critical for legacy interface bridging - while maintaining competitive speed and ultra-small SOT-953 footprint.
Availability
NL17SH08P5T5G is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, portable medical devices, smart energy meters, and other applications requiring stable component supply with extended temperature support and mixed-voltage logic compatibility.
Supply support for NL17SH08P5T5G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, and IoT applications.
The NL17SH08P5T5G belongs to the NL17S logic family - designed specifically for high-speed, low-power, mixed-voltage interfacing in harsh-environment embedded systems.
FAQ
What is the maximum input voltage the NL17SH08P5T5G can tolerate?
The NL17SH08P5T5G supports DC input voltages from −0.5 V to +7.0 V, regardless of VCC level. This allows safe interfacing of 5.0 V signals into a 3.3 V-powered system without external protection components. The specification is validated per absolute maximum ratings and confirmed in the datasheet's VIN parameter table.
Does the NL17SH08P5T5G support operation at 2.0 V supply?
Yes, the NL17SH08P5T5G is fully specified down to 2.0 V VCC, with guaranteed VIH/VIL thresholds, propagation delay (tPD ≤ 10.5 ns at 2.0 V), and output drive performance. This enables use in low-voltage battery-powered systems where rail voltage may sag below 2.5 V during discharge.
Is the NL17SH08P5T5G pin-compatible with standard 2-input AND gates in SOT-23-5?
No - the NL17SH08P5T5G uses SOT-953 (5-pin, 0.35 mm pitch), which is physically smaller and not mechanically or electrically pin-compatible with SOT-23-5 (0.65 mm pitch). Pin assignments differ: SOT-953 places GND at Pin 3 and VCC at Pin 4, whereas SOT-23-5 typically places GND at Pin 1 and VCC at Pin 5.
What is the thermal performance limit for continuous operation of the NL17SH08P5T5G?
The NL17SH08P5T5G is rated for continuous operation from −55°C to +125°C ambient temperature. Its junction temperature must not exceed +150°C under bias. Derating curves in the datasheet confirm 117.8 years MTTF at 80°C junction temperature, supporting long-life deployment in sealed industrial enclosures.
Can the NL17SH08P5T5G drive a 50 pF capacitive load at full speed?
Yes - the NL17SH08P5T5G is characterized up to 50 pF load capacitance. At VCC = 5.0 V, tPD increases to 9.0 ns (max) under those conditions, remaining well within high-speed logic timing budgets. Layout best practices (short traces, ground plane) are recommended to maintain signal integrity.
NL17SH08P5T5G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SH
- Package/Case:
- SOT-953
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- AND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- 0.5V ~ 1.65V
- Input Logic Level - High:
- 1.5V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 7.9ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-953
NL17SH08P5T5G FAQ
1.How can I place an order for NL17SH08P5T5G through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SH08P5T5G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SH08P5T5G reliable?
The price and inventory of NL17SH08P5T5G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SH08P5T5G is usually 5 days.
3.What payment methods are accepted for NL17SH08P5T5G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SH08P5T5G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL17SH08P5T5G?
NL17SH08P5T5G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SH08P5T5G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SH08P5T5G?
For technical support, including NL17SH08P5T5G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SH08P5T5G requirements.
6.How does Aetrix verify that NL17SH08P5T5G is sourced from the original manufacturer or authorized distributors?
All NL17SH08P5T5G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SH08P5T5G meets industry standards.
7.What is the process for return or replacement of NL17SH08P5T5G?
All NL17SH08P5T5G units undergo pre-shipment inspection (PSI). If there is an issue with NL17SH08P5T5G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SH08P5T5G part is unused and in its original packaging.
Return procedure for NL17SH08P5T5G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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