onsemi NL17SZ00XV5T2G
- Part No.:
- NL17SZ00XV5T2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- SOT-553
- Datasheet:
-
NL17SZ00XV5T2G.pdf
- Description:
- IC GATE NAND 1CH 2-INP SOT553
- Quantity:
- Payment:

- Shipping:

Inventory:1,763
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Product details
Overview
NL17SZ00XV5T2G from onsemi is a single 2-input NAND gate logic IC in SOT-553 package, operating from 1.65 V to 5.5 V supply, delivering 2.4 ns propagation delay at 5 V, with 24 mA output drive at 3.0 V, and overvoltage-tolerant inputs/outputs up to 5.5 V - used in level-shifting, signal inversion, and enable control in portable power management circuits.
For engineers reviewing the NL17SZ00XV5T2G datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage range compatibility, IOFF partial power-down support, input overvoltage tolerance, and SOT-553 footprint constraints for space-constrained PCB layouts.
Technical Context
The NL17SZ00XV5T2G implements standard CMOS NAND logic with active-low output behavior defined by its truth table (A=H,B=H→Y=L; all other input combinations yield Y=H). It supports tri-state-compatible operation via IOFF functionality during power-down, preventing back-driving of powered rails.
Its AC performance is characterized across VCC ranges: tPLH/tPHL = 2.4 ns (typ) at 3.0–3.6 V with 15 pF load, and 2.0 ns (typ) at 4.5–5.5 V under same conditions. Input and output capacitance are both 2.5 pF, minimizing switching noise and dynamic loading effects.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| tPD (typ) | 2.4 ns at VCC = 5 V, CL = 15 pF - supports high-speed timing-critical functions such as clock gating and pulse shaping. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives multiple standard TTL or CMOS loads without external buffering. |
| Input Overvoltage | Tolerant to 5.5 V regardless of VCC - allows safe interfacing with higher-voltage peripherals in mixed-supply systems. |
| IOFF | <10 µA at VCC = 0 V - prevents current leakage between unpowered and powered sections in partial-power-down architectures. |
| Operating Temp | −55 °C to +125 °C - qualified for extended industrial and automotive under-hood environments. |
Pinout & Package
SOT-553 (Case 463B), 1.60 mm × 1.20 mm × 0.55 mm body, 0.50 mm pitch, 5-pin surface-mount package with exposed pad not present - optimized for ultra-compact board space and thermal performance in portable electronics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | B | Second logic input; accepts DC voltage up to 5.5 V independent of VCC. |
| 2 | A | First logic input; identical electrical characteristics to Pin 1. |
| 3 | GND | Ground reference for internal circuitry and output return path. |
| 4 | Y | NAND output; actively driven high or low; supports 24 mA sink/source at 3.0 V. |
| 5 | VCC | Positive supply rail; powers internal logic and output stage; range 1.65–5.5 V. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 1.65 V to 5.5 V operation enables drop-in use across legacy and modern low-voltage systems without redesign. |
| Overvoltage-tolerant I/O | Inputs and outputs withstand 5.5 V regardless of VCC, eliminating need for external clamping diodes in mixed-rail interfaces. |
| IOFF protection | Sub-10 µA power-off leakage prevents bus contention and back-powering when VCC is inactive. |
| High drive strength | 24 mA output capability at 3.0 V supports direct fan-out to ≥10 LS-TTL loads or ≥4 CMOS loads. |
| Low dynamic power | CPD = 11 pF at 5.5 V enables <1 mW typical dynamic power at 10 MHz, critical for battery-powered devices. |
Applications
| Power Sequencing Control | USB Interface Enable Logic |
|---|---|
Use Scenario: Controlling power-up order of multiple voltage rails using reset signals and enable lines in PMIC-based systems. IC Role / Device Role / Timing Role: NAND gate configured as active-low enable shaper, combining two control signals to generate synchronized rail activation pulses. Use Value: Eliminates need for discrete resistor networks or larger logic arrays while maintaining precise timing margin via 2.4 ns propagation delay. |
Use Scenario: Enabling/disabling USB data line drivers based on host detection and VBUS presence in portable accessories. IC Role / Device Role / Timing Role: Signal combiner that asserts driver enable only when both VBUS valid and host ready signals are high. Use Value: Prevents spurious data transmission during hot-plug events using overvoltage-tolerant inputs tied directly to 5 V VBUS. |
| IoT Sensor Node Wake-Up Logic | Industrial PLC Input Conditioning |
Use Scenario: Aggregating motion, light, and button inputs to trigger microcontroller wake-up in ultra-low-power sensor nodes. IC Role / Device Role / Timing Role: Low-leakage NAND gate acting as interrupt combiner with IOFF support during deep-sleep mode. Use Value: Maintains sub-µA system standby current while enabling fast (<10 ns) wake-up response via 24 mA drive into MCU interrupt pin. |
Use Scenario: Debouncing and polarity correction of 24 V industrial switch inputs before feeding to 3.3 V FPGA I/O banks. IC Role / Device Role / Timing Role: Level-translating logic buffer with 5.5 V tolerant inputs accepting raw 24 V signals through resistive dividers. Use Value: Reduces BOM count by replacing dedicated level translators and Schmitt triggers with a single 1.65–5.5 V compatible gate. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NAND gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G00DBVR | Same SOT-553 package, but VCC min = 1.65 V, max = 5.5 V; tPD = 3.7 ns (typ) at 3.3 V; IOH/IOL = ±32 mA at 3.3 V. | Higher drive strength but slower propagation at lower VCC; no explicit IOFF specification in datasheet. | Select when higher output current is required and partial power-down is not needed. |
| 74AUP1G00GW,125 | SOT-353 (SC-88A) package; VCC = 0.8–3.6 V; tPD = 2.3 ns (typ) at 3.0 V; IOH/IOL = ±4 mA at 3.0 V. | Lower voltage range and reduced drive limit it to ultra-low-power 1.8/3.3 V-only systems; smaller footprint but incompatible pinout. | Select for battery-powered 3.3 V designs where minimal static current (0.9 µA ICC) outweighs drive requirements. |
Compared with SN74LVC1G00DBVR and 74AUP1G00GW,125, the NL17SZ00XV5T2G uniquely balances 2.4 ns speed, 24 mA drive, IOFF protection, and 5.5 V overvoltage tolerance in SOT-553 - making it optimal for mixed-voltage industrial and automotive subsystems requiring robustness and layout efficiency.
Availability
NL17SZ00XV5T2G is available at Aetrix Electronics and suitable for power sequencing control, USB interface enable logic, IoT sensor node wake-up logic, and industrial PLC input conditioning requiring stable component supply across automotive, industrial, and portable electronics programs.
Supply support for NL17SZ00XV5T2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon and SiC solutions for automotive, industrial, cloud, and IoT applications.
The NL17SZ00XV5T2G belongs to onsemi's NanoLogic™ family of ultra-small logic gates designed for space-constrained, low-power, and mixed-voltage embedded systems requiring high reliability and wide operating margins.
FAQ
What is the maximum operating temperature for NL17SZ00XV5T2G?
The NL17SZ00XV5T2G is rated for operation from −55 °C to +125 °C, meeting extended industrial and automotive under-hood temperature requirements. This rating is verified per the Recommended Operating Conditions table in the official onsemi datasheet (Rev. 19, January 2026), and applies across the full 1.65 V to 5.5 V VCC range.
Does NL17SZ00XV5T2G support partial power-down protection?
Yes, NL17SZ00XV5T2G features IOFF circuitry that limits power-off leakage current to ≤10 µA when VCC = 0 V, preventing back-current flow from live inputs or outputs into an unpowered device. This is explicitly specified in the DC Electrical Characteristics table and supports safe operation in multi-rail systems.
What is the propagation delay of NL17SZ00XV5T2G at 3.3 V supply?
At VCC = 3.3 V with 15 pF load, the NL17SZ00XV5T2G exhibits tPLH/tPHL = 2.4 ns (typical) and ≤4.7 ns (maximum) over temperature, as confirmed in the AC Electrical Characteristics table. This value is measured under standard test conditions (RL = 1 MΩ, CL = 15 pF) per Figure 3 of the datasheet.
Is NL17SZ00XV5T2G pin-compatible with other SOT-553 logic gates?
No - NL17SZ00XV5T2G uses a non-standard SOT-553 pinout (Pin 1=B, Pin 2=A, Pin 3=GND, Pin 4=Y, Pin 5=VCC) that differs from common 5-pin logic gate arrangements. For example, SN74LVC1G00DBVR uses Pin 1=A, Pin 2=GND, Pin 3=Y, Pin 4=VCC, Pin 5=B. PCB layout must be verified against the exact pin assignment in Figure 2 of the NL17SZ00 datasheet.
What packaging and compliance certifications apply to NL17SZ00XV5T2G?
NL17SZ00XV5T2G is supplied in Pb-free, Halogen-Free/BFR-Free SOT-553 tape-and-reel packaging (4000 units per reel), compliant with RoHS Directive 2011/65/EU. It is not AEC-Q100 qualified - that status applies only to variants with "−Q" suffix (e.g., NL17SZ00XV5T2G−Q); this part is intended for industrial and commercial applications.
NL17SZ00XV5T2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- SOT-553
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- NAND Gate
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- -
- Input Logic Level - High:
- -
- Max Propagation Delay @ V, Max CL:
- 4.3ns @ 5V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-553
NL17SZ00XV5T2G FAQ
1.How can I place an order for NL17SZ00XV5T2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SZ00XV5T2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SZ00XV5T2G reliable?
The price and inventory of NL17SZ00XV5T2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ00XV5T2G is usually 5 days.
3.What payment methods are accepted for NL17SZ00XV5T2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ00XV5T2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL17SZ00XV5T2G?
NL17SZ00XV5T2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SZ00XV5T2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SZ00XV5T2G?
For technical support, including NL17SZ00XV5T2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ00XV5T2G requirements.
6.How does Aetrix verify that NL17SZ00XV5T2G is sourced from the original manufacturer or authorized distributors?
All NL17SZ00XV5T2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ00XV5T2G meets industry standards.
7.What is the process for return or replacement of NL17SZ00XV5T2G?
All NL17SZ00XV5T2G units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ00XV5T2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SZ00XV5T2G part is unused and in its original packaging.
Return procedure for NL17SZ00XV5T2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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