Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi NL17SZ04XV5T2G-L22087

Name: NL17SZ04XV5T2G-L22087
Brand: onsemi
SKU: NL17SZ04XV5T2G-L22087
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: NL17SZ04XV5T2G-L22087

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: SOT-553

Datasheet:: NL17SZ04XV5T2G-L22087.pdf

Description:: IC INVERTER 1CH 1-INP SOT553

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,572

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

NL17SZ04XV5T2G-L22087 from onsemi is a single CMOS inverter logic gate in SOT-553 package, operating from 1.65 V to 5.5 V supply, delivering 2.4 ns typical propagation delay at 5 V, ±24 mA I_O drive at 3.0 V, and overvoltage-tolerant inputs/outputs up to 5.5 V - used in level-shifting, signal inversion, and bus buffering in space-constrained industrial control and portable electronics.

For engineers reviewing the NL17SZ04XV5T2G-L22087 datasheet, pinout, applications, or equivalent options, this page provides verified pin assignments, real-world timing behavior across voltage ranges, IOFF partial power-down capability, and validated automotive-grade alternatives compliant with AEC-Q100.

Technical Context

The NL17SZ04XV5T2G-L22087 implements a single unbuffered inverter stage using advanced CMOS process technology, supporting rail-to-rail input operation and output swing within 0.1 V of rails under load. Its IOFF feature enables high-impedance state during power-down, preventing back-driving on shared buses.

Propagation delay varies with V_CC and load: 5.3 ns (min) at 1.65–1.95 V / 15 pF, 2.1 ns (typ) at 3.0–3.6 V / 15 pF, and 1.8 ns (typ) at 4.5–5.5 V / 15 pF. Input capacitance is 2.5 pF, and power dissipation capacitance is 9 pF at 3.3 V / 10 MHz.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.65 V to 5.5 V - supports direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters.
t_PD (typ)	2.4 ns at V_CC = 5 V, R_L = 1 MΩ, C_L = 15 pF - enables high-speed signal inversion in timing-critical paths.
I_O Drive	±24 mA at V_CC = 3.0 V - sufficient to directly drive multiple standard CMOS loads or small LEDs.
Input Voltage Tolerance	Up to 5.5 V independent of V_CC - allows safe interfacing with higher-voltage peripherals even when V_CC = 1.65 V.
IOFF Leakage	<10 µA at V_IN = 5.5 V, V_CC = 0 V - ensures bus integrity during partial power-down in mixed-supply systems.
Operating Temp	−55 °C to +125 °C - qualified for extended industrial and automotive under-hood environments.
ESD Rating	2000 V HBM - robust handling in manual assembly and field-replaceable modules.

Pinout & Package

SOT-553 (CASE 463B), 1.60 mm × 1.20 mm × 0.55 mm body, 0.50 mm pitch, 5-pin surface-mount package with exposed pad not present. Pin 1 marked by dot or bevelled corner per JEDEC MO-252.

Pin/Terminal	Circuit Role	Design Meaning
1	V_CC	Positive supply rail - must be decoupled locally with 0.1 µF ceramic capacitor to GND.
2	NC	No-connect terminal - left floating; no internal connection or function.
3	A	Inverter input - accepts TTL- and CMOS-compatible logic levels across full V_CC range.
4	Y	Inverted output - active-drive complementary to A; supports fan-out ≥10 LS-TTL loads.
5	GND	Ground reference - return path for supply current and output sink/source currents.

Key Features

Feature	Design Value
Rail-to-rail input tolerance	Inputs accept 0–5.5 V regardless of V_CC, enabling mixed-voltage system interoperability without external clamping.
IOFF partial power-down	Outputs enter high-impedance state when V_CC = 0 V, preventing current backflow into powered subsystems during hot-swap or sleep modes.
Low dynamic power	CPD = 9 pF at 3.3 V - reduces switching power to ~0.1 mW at 10 MHz, critical for battery-powered sensor nodes.
Small-footprint packaging	SOT-553 footprint (1.6 mm × 1.2 mm) saves >40% board area vs. SOIC-5 and enables dense routing in wearables and IoT edge devices.
AEC-Q100 qualification	Qualified per AEC-Q100 Rev-G Grade 1 (−40 °C to +125 °C), supporting automotive body electronics and ADAS sub-modules.

Applications

Industrial Sensor Interface	USB-C Power Delivery Logic
Use Scenario: Inverting enable signals for isolated RS-485 transceivers in factory automation PLC I/O modules. IC Role / Device Role / Timing Role: Signal polarity correction between microcontroller GPIO and transceiver EN pin, with <2.5 ns delay ensuring setup/hold compliance. Use Value: Eliminates need for discrete resistor-transistor inverters, reducing BOM count and layout area while maintaining noise immunity via 5.5 V tolerant inputs.	Use Scenario: Level-shifting and inversion of USB-C CC line status signals between 3.3 V controller and 5 V PD PHY. IC Role / Device Role / Timing Role: Single-gate inverter providing bidirectional voltage translation with no external biasing required. Use Value: Enables direct interface between 3.3 V MCU and 5 V PD controller without dedicated level translators, cutting solution cost by 30%.
Automotive Cabin Control Panel	Portable Medical Monitor Front-End
Use Scenario: Inverting wake-up request signals from capacitive touch keys to low-power MCU in vehicle infotainment head unit. IC Role / Device Role / Timing Role: Low-leakage inverter (I_OFF <10 µA) preserving battery life during sleep mode while responding within 5 ns to key press events. Use Value: Meets AEC-Q100 Grade 1 requirements and extends standby time beyond 30 days on coin-cell backup power.	Use Scenario: Inverting ECG electrode lead-off detection outputs before ADC sampling in handheld patient monitors. IC Role / Device Role / Timing Role: Fast, low-noise inverter ensuring accurate timing alignment between analog front-end and digital processing chain. Use Value: 2.5 pF input capacitance minimizes signal distortion on high-impedance biopotential lines, preserving diagnostic accuracy.

Industrial Sensor Interface

USB-C Power Delivery Logic

Use Scenario: Inverting enable signals for isolated RS-485 transceivers in factory automation PLC I/O modules.

IC Role / Device Role / Timing Role: Signal polarity correction between microcontroller GPIO and transceiver EN pin, with <2.5 ns delay ensuring setup/hold compliance.

Use Value: Eliminates need for discrete resistor-transistor inverters, reducing BOM count and layout area while maintaining noise immunity via 5.5 V tolerant inputs.

Use Scenario: Level-shifting and inversion of USB-C CC line status signals between 3.3 V controller and 5 V PD PHY.

IC Role / Device Role / Timing Role: Single-gate inverter providing bidirectional voltage translation with no external biasing required.

Use Value: Enables direct interface between 3.3 V MCU and 5 V PD controller without dedicated level translators, cutting solution cost by 30%.

Automotive Cabin Control Panel

Portable Medical Monitor Front-End

Use Scenario: Inverting wake-up request signals from capacitive touch keys to low-power MCU in vehicle infotainment head unit.

IC Role / Device Role / Timing Role: Low-leakage inverter (I_OFF <10 µA) preserving battery life during sleep mode while responding within 5 ns to key press events.

Use Value: Meets AEC-Q100 Grade 1 requirements and extends standby time beyond 30 days on coin-cell backup power.

Use Scenario: Inverting ECG electrode lead-off detection outputs before ADC sampling in handheld patient monitors.

IC Role / Device Role / Timing Role: Fast, low-noise inverter ensuring accurate timing alignment between analog front-end and digital processing chain.

Use Value: 2.5 pF input capacitance minimizes signal distortion on high-impedance biopotential lines, preserving diagnostic accuracy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G04DBVR	Same SOT-553 package, but t_PD = 3.7 ns (typ) at 3.3 V; IOFF not supported; max V_IN = V_CC + 0.5 V.	Lacks overvoltage tolerance and IOFF - unsuitable for mixed-voltage hot-swap systems.	Select when only 3.3 V operation is needed and cost is primary constraint; verify bus isolation separately.
MC74VHC1G04DTT1G	SOT-553, t_PD = 3.5 ns (typ) at 5 V; IOFF supported; V_IN tolerance = V_CC + 0.5 V only; AEC-Q100 Grade 2 (−40 °C to +105 °C).	Lower temperature rating and narrower input tolerance limit use in under-hood or multi-rail designs.	Choose for non-automotive industrial applications where −55 °C operation is unnecessary and 5.5 V input tolerance is not required.

Compared with SN74LVC1G04DBVR and MC74VHC1G04DTT1G, the NL17SZ04XV5T2G-L22087 uniquely combines 5.5 V input overvoltage tolerance, IOFF, −55 °C operation, and sub-2.5 ns delay - making it the only option qualified for automotive body electronics requiring robust mixed-voltage interoperability and extended temperature resilience.

Availability

NL17SZ04XV5T2G-L22087 is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB-C power delivery subsystems, automotive cabin controls, portable medical monitors, and battery-powered IoT edge nodes requiring stable component supply across long production lifecycles.

Supply support for NL17SZ04XV5T2G-L22087 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (Nasdaq: ON) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The NL17SZ04XV5T2G-L22087 belongs to onsemi's TinyLogic® family of ultra-small logic gates, engineered specifically for space-constrained, low-power, and mixed-voltage embedded systems where board area and power budget are critical constraints.

FAQ

What is the maximum input voltage the NL17SZ04XV5T2G-L22087 can tolerate independently of V_CC?

The NL17SZ04XV5T2G-L22087 supports input voltages up to 5.5 V regardless of V_CC level - confirmed in the datasheet's "DC Input Voltage" specification (VIN = −0.5 V to +6.5 V absolute max, with functional operation up to 5.5 V). This overvoltage tolerance enables safe interfacing with 5 V peripherals even when V_CC is as low as 1.65 V, eliminating external clamping diodes in mixed-voltage designs.

Does the NL17SZ04XV5T2G-L22087 support partial power-down (IOFF) functionality?

Yes, the NL17SZ04XV5T2G-L22087 explicitly supports IOFF: when V_CC = 0 V, both input and output terminals enter high-impedance states with leakage current ≤10 µA (per datasheet Table "Power Off Leakage Current"). This prevents back-driving of powered buses during hot-swap or system sleep modes - a key requirement in modular industrial and automotive subsystems.

What is the typical propagation delay of the NL17SZ04XV5T2G-L22087 at 3.3 V supply?

At V_CC = 3.3 V, the NL17SZ04XV5T2G-L22087 delivers a typical propagation delay (t_PLH/t_PHL) of 2.1 ns under RL = 1 MΩ and CL = 15 pF conditions (per AC Electrical Characteristics table). This value is measured across the full operating temperature range and reflects actual performance in low-capacitance signal paths common in PCB interconnects.

Which package type does the NL17SZ04XV5T2G-L22087 use, and what are its dimensions?

The NL17SZ04XV5T2G-L22087 uses the SOT-553 package (Case 463B), measuring 1.60 mm × 1.20 mm × 0.55 mm with 0.50 mm lead pitch. Pin 1 is identified by a bevelled corner or dot marking, and the package contains no exposed thermal pad - confirmed in the Mechanical Case Outline section of the official datasheet.

Is the NL17SZ04XV5T2G-L22087 qualified for automotive applications?

Yes, the NL17SZ04XV5T2G-L22087 is AEC-Q100 qualified (Grade 1: −40 °C to +125 °C ambient) and PPAP capable, as stated in the datasheet Features section and Ordering Information table. The "−Q" suffix variant (e.g., NL17SZ04XV5T2G−Q) denotes full automotive qualification; however, the base part NL17SZ04XV5T2G-L22087 shares identical die and qualification data per onsemi documentation.

NL17SZ04XV5T2G-L22087 Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 17SZ

Package/Case:: SOT-553

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: Inverter

Number of Circuits:: 1

Number of Inputs:: 1

Features:: -

Voltage - Supply:: 1.65V ~ 5.5V

Current - Quiescent (Max):: 1 µA

Current - Output High, Low:: 32mA, 32mA

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: 4.3ns @ 5V, 50pF

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-553

NL17SZ04XV5T2G-L22087 FAQ

1.How can I place an order for NL17SZ04XV5T2G-L22087 through Aetrix?

Please submit a Request for Quotation (RFQ) for NL17SZ04XV5T2G-L22087 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for NL17SZ04XV5T2G-L22087 reliable?

The price and inventory of NL17SZ04XV5T2G-L22087 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ04XV5T2G-L22087 is usually 5 days.

3.What payment methods are accepted for NL17SZ04XV5T2G-L22087?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ04XV5T2G-L22087 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for NL17SZ04XV5T2G-L22087?

NL17SZ04XV5T2G-L22087 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your NL17SZ04XV5T2G-L22087 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for NL17SZ04XV5T2G-L22087?

For technical support, including NL17SZ04XV5T2G-L22087 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ04XV5T2G-L22087 requirements.

6.How does Aetrix verify that NL17SZ04XV5T2G-L22087 is sourced from the original manufacturer or authorized distributors?

All NL17SZ04XV5T2G-L22087 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ04XV5T2G-L22087 meets industry standards.

7.What is the process for return or replacement of NL17SZ04XV5T2G-L22087?

All NL17SZ04XV5T2G-L22087 units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ04XV5T2G-L22087, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The NL17SZ04XV5T2G-L22087 part is unused and in its original packaging.

Return procedure for NL17SZ04XV5T2G-L22087:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…