onsemi NL17SZ125MU3TCG
- Part No.:
- NL17SZ125MU3TCG
- Manufacturer:
- onsemi
- Package:
- 6-UFDFN
- Datasheet:
-
NL17SZ125MU3TCG.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 6UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
NL17SZ125MU3TCG from onsemi is a single non-inverting 3-state buffer IC designed for level translation and bus isolation in low-voltage digital systems. It operates from 1.65 V to 5.5 V, delivers 2.3 ns propagation delay at 5 V, supports 24 mA output drive at 3.0 V, and features IOFF partial power-down protection. It is used in portable logic interfacing, I²C bus buffering, and mixed-voltage signal routing.
For engineers reviewing the NL17SZ125MU3TCG datasheet, pinout, applications, or equivalent options, key selection criteria include supply voltage range compatibility, 3-state enable timing (tPZH/tPHZ), overvoltage-tolerant inputs up to 5.5 V, and UDFN6 package thermal performance (θJA = 154 °C/W).
Technical Context
The NL17SZ125MU3TCG implements a single-channel non-inverting buffer with active-low 3-state enable (OE). Its input structure is overvoltage tolerant to 5.5 V regardless of VCC, enabling safe interfacing between 1.8 V, 2.5 V, 3.3 V, and 5 V domains. The IOFF feature disables both input and output leakage paths when VCC = 0 V, preventing back-driving in partial-power-down systems.
Propagation delay (tPLH/tPHL) scales with supply voltage: 4.5–4.8 ns at 4.5–5.5 V (CL = 15 pF), 5.2–5.5 ns at 3.0–3.6 V, and 6.0–10.5 ns at 1.65–1.95 V. Output enable/disable times (tPZH/tPHZ, tPZL/tPLZ) are similarly voltage-dependent, ranging from 2.0–5.8 ns across the operating range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic families |
| tPD (typ) | 2.3 ns at VCC = 5 V, CL = 15 pF - supports high-speed data routing in compact logic interfaces |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives standard CMOS loads and multiple fanouts without external buffers |
| Input Overvoltage | Tolerant to 5.5 V independent of VCC - eliminates need for external clamping diodes in mixed-supply systems |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents current backflow during system sleep or hot-swap events |
| θJA | 154 °C/W (UDFN6) - enables stable operation under 812 mW power dissipation in still air |
| ESD Rating | HBM 2000 V, CDM 1000 V - meets industrial-grade robustness requirements without additional protection circuitry |
Pinout & Package
NL17SZ125MU3TCG is packaged in a 1.0 mm × 1.0 mm, 0.35 mm pitch UDFN6 (Case 517BX) with wettable flanks and Pb-free finish. The package has six terminals: five functional pins and one NC (no-connect) terminal.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE (Active-Low Enable) | Asserting low enables output Y; high places Y in high-impedance state - critical for bus arbitration and shared-line control |
| 2 | A (Input) | Non-inverting data input - accepts overvoltage-tolerant signals up to 5.5 V regardless of VCC setting |
| 3 | GND | Ground reference for all internal circuitry and I/O - must be connected to system ground plane for noise immunity |
| 4 | Y (Output) | Buffered, non-inverted output - provides rail-to-rail swing and 24 mA drive capability at 3.0 V |
| 5 | NC | No internal connection - left unconnected per design; no routing or grounding required |
| 6 | VCC | Positive supply input - powers internal logic and defines output voltage levels; supports 1.65–5.5 V operation |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 1.65 V to 5.5 V operation allows direct integration into battery-powered, USB, and legacy 5 V systems without level shifters |
| Overvoltage-tolerant inputs | Inputs withstand up to 5.5 V even when VCC = 1.65 V - simplifies inter-family communication and reduces BOM count |
| IOFF partial power-down | Blocks current flow through A and Y when VCC = 0 V - essential for hot-plug, power-gating, and low-power standby modes |
| Low propagation delay | 2.3 ns typical at 5 V enables use in high-frequency clock distribution and fast data path isolation |
| UDFN6 footprint | 1.0 mm × 1.0 mm, 0.35 mm pitch - saves >60% board area vs. SC-74A-5 and supports ultra-compact portable designs |
Applications
| USB Peripheral Interface | I²C Bus Isolation |
|---|---|
Use Scenario: Isolating I/O lines between a 3.3 V microcontroller and 5 V USB transceiver while maintaining signal integrity during plug/unplug events. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer providing bidirectional signal pass-through with OE-controlled bus release. Use Value: IOFF protection prevents back-current from 5 V transceiver into powered-down MCU, eliminating risk of latch-up or damage. | Use Scenario: Buffering SDA/SCL lines between 1.8 V sensor nodes and 3.3 V host controller in multi-drop I²C networks. IC Role / Device Role / Timing Role: Voltage-level agnostic repeater that maintains I²C timing budgets via sub-5 ns propagation delay. Use Value: Input overvoltage tolerance allows direct connection to 3.3 V pull-ups while operating at 1.8 V VCC - no external level translators needed. |
| Portable Display Data Routing | FPGA Configuration Interface |
Use Scenario: Routing parallel display data (e.g., RGB or LVDS control signals) from an SoC to a display driver IC in space-constrained wearables. IC Role / Device Role / Timing Role: High-speed, low-skew buffer enabling clean signal edge delivery across short PCB traces. Use Value: 2.3 ns tPD and 2.5 pF input/output capacitance minimize jitter and ensure setup/hold compliance at ≥25 MHz pixel clocks. | Use Scenario: Isolating FPGA configuration pins (e.g., INIT_B, PROGRAM_B) from host processor during power sequencing or firmware updates. IC Role / Device Role / Timing Role: Controlled-enable buffer ensuring FPGA pins remain tri-stated until host asserts valid configuration sequence. Use Value: OE-controlled 3-state output guarantees no unintended drive on FPGA reset/configuration lines - prevents configuration corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Same UDFN6 package, but 1.65–5.5 V VCC range and 3.7 ns tPD at 3.3 V (vs. 2.3 ns at 5 V for NL17SZ125MU3TCG) | Lower drive strength (±24 mA at 3.3 V only); no IOFF support - unsuitable for true partial power-down scenarios | Select when cost sensitivity outweighs need for sub-2.5 ns delay or IOFF; verify thermal derating at 154 °C/W θJA |
| 74LVC1G125GW,125 | SC-70-5 package (2.1 mm × 1.2 mm), 1.65–5.5 V, 3.2 ns tPD at 3.3 V; includes IOFF but higher θJA (320 °C/W) | Larger footprint and lower thermal efficiency than UDFN6 - limits use in thermally dense layouts | Choose only if SC-70-5 is already standardized in design; avoid where board area < 1.2 mm² or junction temp rise > 40 °C is unacceptable |
Compared with SN74LVC1G125DBVR and 74LVC1G125GW,125, the NL17SZ125MU3TCG offers the fastest propagation delay at 5 V, lowest thermal resistance in its class, and guaranteed IOFF behavior - making it optimal for high-speed, mixed-voltage, and power-gated embedded interfaces where timing margin and reliability are critical.
Availability
NL17SZ125MU3TCG is available at Aetrix Electronics and suitable for USB peripheral interface, I²C bus isolation, portable display data routing, FPGA configuration interface, and low-power sensor hub applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for NL17SZ125MU3TCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NL17SZ125MU3TCG belongs to onsemi's NanoLogic™ family of ultra-small, high-performance logic ICs - engineered specifically for space-constrained, low-power, and mixed-voltage digital interface applications in portable and embedded systems.
FAQ
What is the maximum operating temperature range for the NL17SZ125MU3TCG?
The NL17SZ125MU3TCG is rated for operation from −55 °C to +125 °C ambient temperature. This extended range supports deployment in automotive under-hood modules, industrial motor controls, and outdoor IoT gateways where thermal extremes are common. The UDFN6 package's low θJA (154 °C/W) helps maintain junction temperature within safe limits even at full load.
Does the NL17SZ125MU3TCG support level-shifting between different supply voltages?
Yes, the NL17SZ125MU3TCG supports level-shifting: its inputs tolerate up to 5.5 V regardless of VCC, allowing a 1.8 V-powered NL17SZ125MU3TCG to accept 3.3 V or 5 V inputs safely. However, output voltage swing is limited to VCC, so it cannot generate higher output voltages than its supply - it functions as a level translator only in the input direction.
Is the NC pin on the NL17SZ125MU3TCG required to be grounded or left floating?
The NC (pin 5) on the NL17SZ125MU3TCG has no internal connection and must be left unconnected - neither grounded nor tied to VCC. Per onsemi's datasheet and package drawings, routing or terminating this pin introduces no benefit and may risk solder bridging or mechanical stress on the 0.35 mm pitch UDFN6 pad.
How does the IOFF feature of the NL17SZ125MU3TCG improve system reliability?
The IOFF feature of the NL17SZ125MU3TCG disables input and output leakage paths when VCC = 0 V, limiting current to ≤10 µA. This prevents back-driving of powered-down sections - critical in hot-plug peripherals, battery-backed subsystems, and multi-rail power sequencing where one domain may be active while another is off, avoiding latch-up or data corruption.
Can the NL17SZ125MU3TCG be used in automotive applications?
Yes - the NL17SZ125MU3TCG is available in automotive-grade variants (e.g., NL17SZ125DFT2G-Q) qualified to AEC-Q100 Grade 1 (−40 °C to +125 °C) and PPAP capable. While the standard NL17SZ125MU3TCG is not automotive-qualified, its −55 °C to +125 °C operating range and robust ESD/overvoltage specs make it suitable for non-safety-critical automotive infotainment and body electronics with proper qualification oversight.
NL17SZ125MU3TCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-UDFN (1x1)
NL17SZ125MU3TCG FAQ
1.How can I place an order for NL17SZ125MU3TCG through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SZ125MU3TCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SZ125MU3TCG reliable?
The price and inventory of NL17SZ125MU3TCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ125MU3TCG is usually 5 days.
3.What payment methods are accepted for NL17SZ125MU3TCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ125MU3TCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL17SZ125MU3TCG?
NL17SZ125MU3TCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SZ125MU3TCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SZ125MU3TCG?
For technical support, including NL17SZ125MU3TCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ125MU3TCG requirements.
6.How does Aetrix verify that NL17SZ125MU3TCG is sourced from the original manufacturer or authorized distributors?
All NL17SZ125MU3TCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ125MU3TCG meets industry standards.
7.What is the process for return or replacement of NL17SZ125MU3TCG?
All NL17SZ125MU3TCG units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ125MU3TCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SZ125MU3TCG part is unused and in its original packaging.
Return procedure for NL17SZ125MU3TCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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