onsemi NL17SZ125XV5T2G-L22087
- Part No.:
- NL17SZ125XV5T2G-L22087
- Manufacturer:
- onsemi
- Package:
- SOT-553
- Datasheet:
-
NL17SZ125XV5T2G-L22087.pdf
- Description:
- IC BUF NON-INVERT 5.5V SOT553
- Quantity:
- Payment:

- Shipping:

Inventory:2,227
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Product details
Overview
NL17SZ125XV5T2G-L22087 from onsemi is a single non-inverting 3-state buffer IC designed for level-shifting and bus isolation in low-voltage digital systems. It operates from 1.65 V to 5.5 V, delivers 2.3 ns typical propagation delay at 5 V, supports 24 mA output drive at 3.0 V, and features IOFF partial power-down protection. It is used in portable instrumentation data paths where voltage translation and tri-state control are required.
For engineers reviewing the NL17SZ125XV5T2G-L22087 datasheet, pinout, applications, or equivalent options, key selection criteria include VCC range compatibility, 3-state enable timing (tPZH/tPHZ), overvoltage-tolerant inputs up to 5.5 V, and SOT-553-5 package footprint constraints.
Technical Context
The NL17SZ125XV5T2G-L22087 implements a single-channel non-inverting buffer with active-low 3-state output control (OE). Its logic function is defined by a truth table where output Y follows input A when OE is low, and enters high-impedance state when OE is high.
It integrates IOFF circuitry that disables input/output leakage during power-down, enabling safe operation in partial-power-down systems. Input and output pins tolerate voltages up to 5.5 V regardless of VCC, supporting mixed-voltage interfacing without external level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains |
| tPLH / tPHL | 2.0 ns (typ) at VCC = 5 V, CL = 15 pF - supports >200 MHz data rates in short trace applications |
| IOH / IOL | ±24 mA at VCC = 3.0 V - drives standard CMOS loads and small capacitive buses directly |
| Input Voltage Tolerance | −0.5 V to +6.5 V - allows hot-plug and mixed-supply interface without clamping diodes |
| IOFF Leakage | 1.0 µA max at VCC = 0 V - prevents back-driving powered-down sections of system |
| Operating Temp | −55 °C to +125 °C - qualified for extended industrial and automotive under-hood environments |
| ESD Rating | 2000 V HBM - meets robustness requirements for board-level handling and assembly |
Pinout & Package
SOT-553-5 (Case 463B), 1.60 mm × 1.20 mm × 0.55 mm body, 0.50 mm pitch, 5-terminal surface-mount package with exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OE | Output Enable (active-low) | Asserting low enables buffer output; high forces Y into high-impedance state |
| 2 - A | Non-inverting Data Input | Accepts logic levels compatible with VCC supply; tolerant to 5.5 V regardless of VCC |
| 3 - GND | Ground Reference | Primary return path for supply current and signal reference; must be low-impedance |
| 4 - Y | Buffered Output | Drives downstream logic; exhibits 2.5 pF typical output capacitance and ±24 mA drive |
| 5 - VCC | Positive Supply | Supplies internal logic and output stage; decoupling capacitor required within 1 cm |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (1.65–5.5 V) | Eliminates need for separate level translators when interfacing 1.8 V controllers to 3.3 V peripherals |
| 2.3 ns tPD at 5 V | Enables use in high-speed control lines such as SPI clock or address strobes with minimal skew |
| IOFF partial power-down | Prevents current flow between powered and unpowered sections-critical for hot-swap subsystems |
| Overvoltage-tolerant I/O | Allows direct connection to 5 V buses even when VCC = 1.8 V, avoiding external clamps or resistors |
| AEC-Q100 qualified option available | Supports automotive infotainment and ADAS modules requiring PPAP documentation and stress testing |
Applications
| Industrial Sensor Interface | Portable Medical Device Bus Isolation |
|---|---|
|
Use Scenario: Isolating analog-to-digital converter (ADC) data lines from a low-power microcontroller during sleep mode. IC Role / Device Role / Timing Role: 3-state buffer isolates ADC output bus when MCU is in deep-sleep; OE controlled by wake-up signal. Use Value: Prevents bus contention and leakage current during sleep, extending battery life by reducing quiescent current to <1 µA. |
Use Scenario: Level-shifting UART signals between a 1.8 V Bluetooth SoC and a 3.3 V ECG front-end ASIC. IC Role / Device Role / Timing Role: Non-inverting buffer translates logic levels bidirectionally while maintaining signal integrity at 1 Mbps. Use Value: Eliminates discrete resistor-divider networks and saves PCB area in space-constrained wearable enclosures. |
| Automotive Body Control Module | Test Equipment Signal Routing |
|
Use Scenario: Enabling/disabling sensor data lanes (e.g., door latch status) based on vehicle ignition state. IC Role / Device Role / Timing Role: OE tied to ignition rail; buffers isolate inactive sensors to reduce EMI and meet ISO 11452-4 immunity targets. Use Value: Meets AEC-Q100 Grade 1 temperature and ESD requirements without additional protection components. |
Use Scenario: Multiplexing multiple DUT signals onto shared test fixture channels using programmable enable control. IC Role / Device Role / Timing Role: Tri-state outputs allow dynamic reconfiguration of signal paths without physical switching. Use Value: Reduces fixture complexity and improves test repeatability by eliminating mechanical relay wear-out. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Wider operating range (1.65–5.5 V same), but tPD = 3.7 ns (typ) at 3.3 V; no IOFF support | Lacks partial power-down protection; unsuitable for systems with unpowered rails | Select when IOFF is not required and cost is primary driver; verify layout accommodates larger SC-70-5 footprint |
| 74AUP1G125GW,125 | Lower ICC (0.9 µA max), but VCC limited to 0.8–3.6 V; tPD = 2.3 ns at 3.0 V | Not rated for 5 V interfaces; incompatible with mixed 5 V/3.3 V systems | Choose only for ultra-low-power 3.3 V-only designs; confirm absence of 5 V signals upstream/downstream |
Compared with SN74LVC1G125DBVR and 74AUP1G125GW,125, the NL17SZ125XV5T2G-L22087 uniquely combines 5.5 V overvoltage tolerance, IOFF, and sub-2.5 ns propagation delay in a 1.6 mm × 1.2 mm SOT-553 package-making it optimal for compact, mixed-voltage, hot-pluggable systems.
Availability
NL17SZ125XV5T2G-L22087 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable medical device bus isolation, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for NL17SZ125XV5T2G-L22087 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon solutions for automotive, industrial, cloud, and medical markets.
The NL17SZ125XV5T2G-L22087 belongs to the NanoLogic® family of ultra-small logic devices, engineered for space-constrained, low-power, mixed-voltage digital signal routing in portable and harsh-environment applications.
FAQ
What is the maximum operating voltage for NL17SZ125XV5T2G-L22087 inputs and outputs?
The NL17SZ125XV5T2G-L22087 supports DC input and output voltages from −0.5 V to +6.5 V, independent of VCC. This overvoltage tolerance allows safe interfacing with 5 V buses even when VCC is as low as 1.65 V, eliminating external clamping diodes in mixed-voltage systems.
Does NL17SZ125XV5T2G-L22087 support partial power-down functionality?
Yes, the NL17SZ125XV5T2G-L22087 includes IOFF circuitry that disables input and output leakage paths when VCC = 0 V. This feature prevents current backflow into powered sections of the system, making it suitable for hot-plug and modular subsystem architectures.
What is the typical propagation delay of NL17SZ125XV5T2G-L22087 at 3.3 V supply?
At VCC = 3.3 V, RL = 1 MΩ, and CL = 15 pF, the NL17SZ125XV5T2G-L22087 exhibits a typical propagation delay (tPLH/tPHL) of 2.5 ns. This value is confirmed in the AC Electrical Characteristics table on page 5 of the official datasheet.
Which package does NL17SZ125XV5T2G-L22087 use, and what are its dimensions?
NL17SZ125XV5T2G-L22087 uses the SOT-553-5 package (Case 463B), measuring 1.60 mm × 1.20 mm × 0.55 mm with 0.50 mm lead pitch. Pin 1 orientation is marked with a dot or notch per Figure 2 on page 2 of the datasheet.
Is NL17SZ125XV5T2G-L22087 qualified for automotive applications?
The base NL17SZ125XV5T2G is not automotive-qualified, but the -Q suffix variant (e.g., NL17SZ125XV5T2G-Q) is AEC-Q100 Grade 1 qualified and PPAP capable. The L22087 lot code indicates standard commercial-grade material unless otherwise specified in order documentation.
NL17SZ125XV5T2G-L22087 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- SOT-553
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-553
NL17SZ125XV5T2G-L22087 FAQ
1.How can I place an order for NL17SZ125XV5T2G-L22087 through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SZ125XV5T2G-L22087 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SZ125XV5T2G-L22087 reliable?
The price and inventory of NL17SZ125XV5T2G-L22087 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ125XV5T2G-L22087 is usually 5 days.
3.What payment methods are accepted for NL17SZ125XV5T2G-L22087?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ125XV5T2G-L22087 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL17SZ125XV5T2G-L22087?
NL17SZ125XV5T2G-L22087 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SZ125XV5T2G-L22087 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SZ125XV5T2G-L22087?
For technical support, including NL17SZ125XV5T2G-L22087 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ125XV5T2G-L22087 requirements.
6.How does Aetrix verify that NL17SZ125XV5T2G-L22087 is sourced from the original manufacturer or authorized distributors?
All NL17SZ125XV5T2G-L22087 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ125XV5T2G-L22087 meets industry standards.
7.What is the process for return or replacement of NL17SZ125XV5T2G-L22087?
All NL17SZ125XV5T2G-L22087 units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ125XV5T2G-L22087, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SZ125XV5T2G-L22087 part is unused and in its original packaging.
Return procedure for NL17SZ125XV5T2G-L22087:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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