onsemi NL17SZ17DBVT1G
- Part No.:
- NL17SZ17DBVT1G
- Manufacturer:
- onsemi
- Package:
- SC-74A, SOT-753
- Datasheet:
-
NL17SZ17DBVT1G.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC74A
- Quantity:
- Payment:

- Shipping:

Inventory:3,612
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Product details
Overview
NL17SZ17DBVT1G from onsemi is a single non-inverting Schmitt trigger buffer in SC-74A (SOT-23-5) package, operating from 1.65 V to 5.5 V supply, delivering 3.7 ns typical propagation delay at 5 V, ±24 mA drive capability at 3.0 V, and input hysteresis up to 1.7 V - used for noise-immune signal conditioning in industrial sensor interfaces and low-voltage logic level translation.
For engineers reviewing the NL17SZ17DBVT1G datasheet, pinout, applications, or equivalent options, this page provides verified pin assignments, real-world timing behavior under 15 pF load, Schmitt threshold values across voltage rails, IOFF partial power-down support, and AEC-Q100-qualified alternatives for automotive-grade designs.
Technical Context
The NL17SZ17DBVT1G implements a single-channel non-inverting buffer with built-in Schmitt-trigger input hysteresis, enabling robust noise rejection on slow or noisy digital signals. Its input thresholds (VT+ = 1.9–3.6 V, VT− = 0.6–1.9 V at VCC = 3.0–5.5 V) provide ≥0.4 V hysteresis across full supply range.
It supports tri-state-compatible operation via IOFF circuitry that disables I/O leakage when VCC = 0 V, and features overvoltage-tolerant inputs/outputs up to 5.5 V independent of supply rail - allowing safe interfacing between mixed-voltage domains such as 1.8 V logic driving 3.3 V or 5 V systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters. |
| tPD (typ) | 3.7 ns at VCC = 5 V, RL = 1 MΩ, CL = 15 pF - ensures minimal delay in high-speed clock/data buffering applications. |
| IOH/IOL | ±24 mA at VCC = 3.0 V - drives standard TTL loads or multiple CMOS inputs without external buffers. |
| Input Hysteresis | 0.7 V (min) to 1.7 V (max) - rejects noise spikes up to ±850 mV on input lines in industrial environments. |
| IOFF Leakage | ≤10 µA at VCC = 0 V - prevents back-powering and signal contention during partial power-down sequences. |
| ESD Rating | HBM ±2000 V, CDM ±1000 V - meets IEC 61000-4-2 Level 3 requirements for board-level ESD immunity. |
| Operating Temp | −55 °C to +125 °C - qualified for extended temperature operation in automotive engine control and industrial PLC modules. |
Pinout & Package
Package: SC-74A (SOT-23-5), 3.00 mm × 1.50 mm × 0.95 mm body, 0.95 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (NC) | No-connect terminal | Internally unconnected; must be left floating or tied to GND per layout best practice - no electrical function. |
| 2 (A) | Input signal | Schmitt-triggered non-inverting input; accepts DC voltages from 0 V to 5.5 V regardless of VCC value. |
| 3 (GND) | Ground reference | Primary return path for supply current and output sink current; requires low-impedance PCB connection. |
| 4 (Y) | Output signal | Non-inverted buffered output with rail-to-rail swing; capable of sourcing/sinking ±24 mA at 3.0 V. |
| 5 (VCC) | Positive supply | Power rail input; decoupling capacitor (0.1 µF ceramic) required within 2 mm of pin for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger input | Provides 0.4–1.7 V hysteresis to reject noise on slow-rising signals like mechanical switch debouncing or sensor outputs. |
| IOFF partial power-down | Enables hot-plug compatibility and system-level power sequencing by blocking I/O leakage when VCC = 0 V. |
| Overvoltage-tolerant I/O | Accepts input/output signals up to 5.5 V even when VCC = 1.65 V - eliminates need for external clamping diodes. |
| Low dynamic power | CPD = 9–11 pF enables <1 µW no-load power at 1 MHz and 3.3 V - suitable for battery-powered IoT edge nodes. |
| AEC-Q100 qualification | Qualified to Grade 1 (−40 °C to +125 °C) with PPAP documentation support - approved for automotive infotainment and ADAS subsystems. |
Applications
| Industrial Sensor Interface | Low-Voltage Logic Translation |
|---|---|
|
Use Scenario: Conditioning analog sensor outputs (e.g., thermistor, RTD, or Hall-effect switches) before ADC sampling or microcontroller GPIO capture. IC Role / Device Role / Timing Role: Schmitt-trigger buffer cleans slow, noisy edges and provides clean digital transitions to MCU interrupt pins. Use Value: Eliminates software debouncing overhead and prevents false triggering due to EMI-induced glitches on long PCB traces. |
Use Scenario: Interfacing 1.8 V FPGA I/O banks with 3.3 V peripheral UARTs or SPI flash memory. IC Role / Device Role / Timing Role: Non-inverting level shifter with rail-to-rail output swing and sub-4 ns delay preserves timing margins. Use Value: Enables bidirectional signal integrity without direction-control logic or external resistors - reduces BOM count by one component. |
| Automotive Body Control Module | Consumer Wearable Power Sequencing |
|
Use Scenario: Debouncing door latch or seatbelt switch inputs in BCMs operating across −40 °C to +125 °C ambient. IC Role / Device Role / Timing Role: AEC-Q100-qualified Schmitt buffer with IOFF ensures safe isolation during sleep/wake transitions. Use Value: Meets ISO 16750-2 pulse test requirements and avoids wake-up false triggers caused by load-dump transients. |
Use Scenario: Enabling/disabling power rails in compact wearables using microcontroller GPIO with weak drive strength. IC Role / Device Role / Timing Role: Buffer amplifies MCU output to reliably drive MOSFET gate drivers or PMIC enable inputs. Use Value: Delivers 24 mA sink/source at 1.8 V supply - sufficient to charge/discharge gate capacitance faster than MCU GPIO alone. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt-trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Same SC-70-5 (SC-74A) package; lower hysteresis (0.2 V typ), no IOFF, max VCC = 5.5 V. | Lacks partial power-down protection; unsuitable for hot-swap or multi-rail sequencing where VCC may be off. | Select when cost sensitivity outweighs IOFF requirement and ambient temperature stays ≤85 °C. |
| MC74VHC1G17DTT1G | Same SC-74A package; higher ICC (10 µA max vs. 1 µA), no AEC-Q100 qualification, VHCT-compatible thresholds. | Not automotive-qualified; hysteresis optimized for 3.3 V/5 V only - less effective below 2.5 V. | Prefer for legacy 5 V systems requiring tighter VIH/VIL matching to older TTL families. |
Compared with SN74LVC1G17DBVR and MC74VHC1G17DTT1G, the NL17SZ17DBVT1G uniquely combines AEC-Q100 qualification, IOFF-enabled partial power-down, and wide-voltage hysteresis (down to 1.65 V), making it the only choice for automotive-grade, mixed-supply, or ultra-low-power industrial designs requiring guaranteed noise immunity.
Availability
NL17SZ17DBVT1G is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body control modules, low-voltage logic translation, and wearable power sequencing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NL17SZ17DBVT1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, medical, and IoT applications.
The NL17SZ17DBVT1G belongs to onsemi's TinyLogic® family of ultra-small logic devices designed for space-constrained, low-power, and noise-sensitive embedded systems requiring robust signal integrity.
FAQ
What is the pin 1 marking orientation for NL17SZ17DBVT1G in SC-74A tape-and-reel packaging?
The NL17SZ17DBVT1G uses SC-74A (SOT-23-5) packaging with pin 1 identified by a dot or notch on the top surface, located adjacent to the leadframe tab side. Per onsemi's ordering information, the marking code "AM" appears on the device body, and pin 1 orientation follows Q4 quadrant placement in tape-and-reel - confirmed in the device's mechanical drawing CASE 318BQ.
Does NL17SZ17DBVT1G support true tri-state operation?
No, the NL17SZ17DBVT1G does not feature an output-enable (OE) pin or internal tri-state logic. It operates exclusively as a non-inverting buffer. However, its IOFF circuitry provides partial power-down protection: when VCC = 0 V, both input and output terminals enter high-impedance mode with ≤10 µA leakage - functionally isolating the device without requiring external OE control.
What is the minimum input rise/fall time supported by NL17SZ17DBVT1G across its operating voltage range?
The NL17SZ17DBVT1G imposes no minimum input edge rate - the recommended operating conditions specify "No Limit" for tr/tf across all VCC ranges (1.65–1.95 V, 2.3–2.7 V, 3.0–3.6 V, and 4.5–5.5 V). This allows reliable operation with very slow-switching signals such as thermistor-based comparators or mechanical switch closures, leveraging its Schmitt-trigger hysteresis for clean output transitions.
Can NL17SZ17DBVT1G be used to interface a 5 V microcontroller with a 1.8 V FPGA input?
Yes - the NL17SZ17DBVT1G's overvoltage-tolerant inputs accept up to 5.5 V regardless of VCC level. Set VCC = 1.8 V to match the FPGA's I/O voltage, connect the 5 V MCU output directly to pin 2 (A), and take the buffered 1.8 V-compatible output from pin 4 (Y). No external resistors or level-shifting components are needed, preserving signal integrity and timing margin.
Is NL17SZ17DBVT1G pin-compatible with other TinyLogic® Schmitt buffers in SC-74A packages?
Yes - the NL17SZ17DBVT1G shares identical SC-74A pinout (pin 1 = NC, pin 2 = A, pin 3 = GND, pin 4 = Y, pin 5 = VCC) with other onsemi TinyLogic® Schmitt buffers including NL17SZ14 (inverter) and NL17SZ74 (D-flip-flop), enabling drop-in replacement in existing layouts where functional change is acceptable and PCB footprint reuse is desired.
NL17SZ17DBVT1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 17SZ
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74A
NL17SZ17DBVT1G FAQ
1.How can I place an order for NL17SZ17DBVT1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NL17SZ17DBVT1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NL17SZ17DBVT1G reliable?
The price and inventory of NL17SZ17DBVT1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NL17SZ17DBVT1G is usually 5 days.
3.What payment methods are accepted for NL17SZ17DBVT1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NL17SZ17DBVT1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NL17SZ17DBVT1G?
NL17SZ17DBVT1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NL17SZ17DBVT1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NL17SZ17DBVT1G?
For technical support, including NL17SZ17DBVT1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NL17SZ17DBVT1G requirements.
6.How does Aetrix verify that NL17SZ17DBVT1G is sourced from the original manufacturer or authorized distributors?
All NL17SZ17DBVT1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NL17SZ17DBVT1G meets industry standards.
7.What is the process for return or replacement of NL17SZ17DBVT1G?
All NL17SZ17DBVT1G units undergo pre-shipment inspection (PSI). If there is an issue with NL17SZ17DBVT1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NL17SZ17DBVT1G part is unused and in its original packaging.
Return procedure for NL17SZ17DBVT1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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